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envelope-from=bin.meng@processmission.com; helo=TYDPR03CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org PolarFire SoC software selects 64-bit ADMA descriptors for the Cadence SDHCI controller. The controller supports those descriptors, but the Cadence property remains disabled by default for other integrations. Enable the bus64bit property from the PolarFire SoC so the generic SDHCI descriptor engine can execute 64-bit ADMA transfers. Signed-off-by: Bin Meng Tested-by: Conor Dooley --- (no changes since v2) Changes in v2: - New hw/riscv/microchip_pfsoc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index d0d8c8f84c..3d1b3246db 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -193,6 +193,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "sd-controller", &s->sdhci, TYPE_CADENCE_SDHCI); + object_property_set_bool(OBJECT(&s->sdhci), "bus64bit", true, + &error_abort); object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); } -- 2.53.0