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envelope-from=bin.meng@processmission.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org U-Boot requests the PolarFire SoC device serial number during board late initialization. The IOSCB previously rejected every request, so board setup could not complete. Model the System Services control registers and byte-addressable mailbox. Obtain the 128-bit serial number from an optional device property, using a deterministic value when it is not configured. Return an explicit failure for unsupported services and reset the new runtime state with the rest of the device. Signed-off-by: Bin Meng Tested-by: Conor Dooley --- (no changes since v3) Changes in v3: - Decode the seven-bit opcode and nine-bit mailbox word offset - Bound serial-number responses to the documented 2 KiB mailbox - Mirror the current control flags in the status register - Use default access sizing for the control and mailbox windows include/hw/misc/mchp_pfsoc_ioscb.h | 6 ++ hw/misc/mchp_pfsoc_ioscb.c | 156 +++++++++++++++++++++++++---- 2 files changed, 144 insertions(+), 18 deletions(-) diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h index 9687ea25b1..aa108d2d88 100644 --- a/include/hw/misc/mchp_pfsoc_ioscb.h +++ b/include/hw/misc/mchp_pfsoc_ioscb.h @@ -25,6 +25,8 @@ #include "hw/core/sysbus.h" +#define MCHP_PFSOC_IOSCB_MAILBOX_SIZE 0x800 + typedef struct MchpPfSoCIoscbState { SysBusDevice parent; MemoryRegion container; @@ -47,6 +49,10 @@ typedef struct MchpPfSoCIoscbState { MemoryRegion cfm_sgmii; MemoryRegion bc_sgmii; MemoryRegion io_calib_sgmii; + uint32_t services_cr; + uint32_t services_sr; + uint8_t mailbox_data[MCHP_PFSOC_IOSCB_MAILBOX_SIZE]; + char *serial_number; qemu_irq irq; } MchpPfSoCIoscbState; diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c index 09b702e520..850125c8b4 100644 --- a/hw/misc/mchp_pfsoc_ioscb.c +++ b/hw/misc/mchp_pfsoc_ioscb.c @@ -25,6 +25,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" #include "hw/core/sysbus.h" #include "hw/misc/mchp_pfsoc_ioscb.h" @@ -37,6 +38,9 @@ #define IOSCB_CCC_REG_SIZE 0x2000000 #define IOSCB_CTRL_REG_SIZE 0x800 #define IOSCB_QSPIXIP_REG_SIZE 0x200 +#define IOSCB_SERIAL_NUMBER_SIZE 16U +#define IOSCB_DEFAULT_SERIAL_NUMBER "0123456789abcdef" +#define IOSCB_PROP_SERIAL_NUMBER "serial-number" /* @@ -186,33 +190,88 @@ static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -#define SERVICES_CR 0x50 -#define SERVICES_SR 0x54 -#define SERVICES_STATUS_SHIFT 16 +#define SERVICES_CR 0x50 +#define SERVICES_CR_REQUEST BIT(0) +#define SERVICES_CR_NOTIFY BIT(3) +#define SERVICES_CR_COMMAND_SHIFT 16 +#define SERVICES_CR_COMMAND_WIDTH 16 +#define SERVICES_CR_COMMAND_MASK \ + MAKE_64BIT_MASK(SERVICES_CR_COMMAND_SHIFT, SERVICES_CR_COMMAND_WIDTH) +#define SERVICES_CR_MASK \ + (SERVICES_CR_REQUEST | SERVICES_CR_NOTIFY | SERVICES_CR_COMMAND_MASK) +#define SERVICES_SR 0x54 +#define SERVICES_SR_CONTROL_MASK 0xf +#define SERVICES_SR_STATUS_SHIFT 16 +#define SERVICES_COMMAND_SERIAL_NUMBER 0 +#define SERVICES_COMMAND_OPCODE_MASK 0x7f +#define SERVICES_COMMAND_MAILBOX_SHIFT 7 +#define SERVICES_COMMAND_MAILBOX_MASK 0x1ff +#define SERVICES_STATUS_SUCCESS 0 +#define SERVICES_STATUS_FAILED 1 + +static void services_cr_write(MchpPfSoCIoscbState *s, uint32_t value) +{ + uint32_t command; + uint32_t opcode; + uint32_t response_offset; + uint32_t status = SERVICES_STATUS_FAILED; + + if (device_is_in_reset(DEVICE(s)) || + !(value & SERVICES_CR_REQUEST)) { + return; + } + + /* + * System services complete synchronously in this model, so clear the + * request bit before exposing the response to the guest. + */ + s->services_cr &= ~SERVICES_CR_REQUEST; + + command = (value & SERVICES_CR_COMMAND_MASK) >> + SERVICES_CR_COMMAND_SHIFT; + opcode = command & SERVICES_COMMAND_OPCODE_MASK; + response_offset = ((command >> SERVICES_COMMAND_MAILBOX_SHIFT) & + SERVICES_COMMAND_MAILBOX_MASK) * sizeof(uint32_t); + if (opcode == SERVICES_COMMAND_SERIAL_NUMBER && + response_offset <= sizeof(s->mailbox_data) - IOSCB_SERIAL_NUMBER_SIZE) { + /* + * The descriptor contains a seven-bit opcode and a nine-bit mailbox + * word offset. Return the 128-bit serial number at that address. + * See section 3 of the PolarFire System Services User Guide. + */ + memset(&s->mailbox_data[response_offset], 0, + IOSCB_SERIAL_NUMBER_SIZE); + memcpy(&s->mailbox_data[response_offset], + s->serial_number, strlen(s->serial_number)); + status = SERVICES_STATUS_SUCCESS; + } + + s->services_sr = status << SERVICES_SR_STATUS_SHIFT; + qemu_irq_raise(s->irq); +} static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset, unsigned size) { - uint32_t val = 0; + MchpPfSoCIoscbState *s = opaque; + uint32_t value; - switch (offset) { + switch (offset & ~3ULL) { + case SERVICES_CR: + value = s->services_cr; + break; case SERVICES_SR: - /* - * Although some services have no error codes, most do. All services - * that do implement errors, begin their error codes at 1. Treat all - * service requests as failures & return 1. - * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services" - * user guide for more information on service error codes. - */ - val = 1u << SERVICES_STATUS_SHIFT; + value = s->services_sr | + (s->services_cr & SERVICES_SR_CONTROL_MASK); break; default: qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " "(size %d, offset 0x%" HWADDR_PRIx ")\n", __func__, size, offset); + return 0; } - return val; + return extract32(value, (offset & 3) * 8, size * 8); } static void mchp_pfsoc_ctrl_write(void *opaque, hwaddr offset, @@ -220,15 +279,22 @@ static void mchp_pfsoc_ctrl_write(void *opaque, hwaddr offset, { MchpPfSoCIoscbState *s = opaque; - switch (offset) { + switch (offset & ~3ULL) { case SERVICES_CR: - qemu_irq_raise(s->irq); + s->services_cr = deposit32(s->services_cr, (offset & 3) * 8, + size * 8, value) & SERVICES_CR_MASK; + if (offset == SERVICES_CR) { + services_cr_write(s, s->services_cr); + } + break; + case SERVICES_SR: break; default: qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " "(size %d, value 0x%" PRIx64 ", offset 0x%" HWADDR_PRIx ")\n", __func__, size, value, offset); + break; } } @@ -238,11 +304,62 @@ static const MemoryRegionOps mchp_pfsoc_ctrl_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +/* + * The System Controller uses the mailbox as a byte-addressable shared buffer + * for service command payloads and responses. + */ +static uint64_t mchp_pfsoc_mailbox_read(void *opaque, hwaddr offset, + unsigned size) +{ + MchpPfSoCIoscbState *s = opaque; + + return ldn_le_p(&s->mailbox_data[offset], size); +} + +static void mchp_pfsoc_mailbox_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + MchpPfSoCIoscbState *s = opaque; + + stn_le_p(&s->mailbox_data[offset], size, value); +} + +static const MemoryRegionOps mchp_pfsoc_mailbox_ops = { + .read = mchp_pfsoc_mailbox_read, + .write = mchp_pfsoc_mailbox_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void mchp_pfsoc_ioscb_reset(DeviceState *dev) +{ + MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev); + + s->services_cr = 0; + s->services_sr = 0; + memset(s->mailbox_data, 0, sizeof(s->mailbox_data)); + qemu_irq_lower(s->irq); +} + +static const Property mchp_pfsoc_ioscb_properties[] = { + DEFINE_PROP_STRING(IOSCB_PROP_SERIAL_NUMBER, + MchpPfSoCIoscbState, serial_number), +}; + static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) { MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + /* Use a deterministic identity when no serial number is configured */ + if (!s->serial_number) { + s->serial_number = g_strdup(IOSCB_DEFAULT_SERIAL_NUMBER); + } + if (strlen(s->serial_number) > IOSCB_SERIAL_NUMBER_SIZE) { + error_setg(errp, "The serial number can't be longer than %u bytes", + IOSCB_SERIAL_NUMBER_SIZE); + return; + } + memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE); sysbus_init_mmio(sbd, &s->container); @@ -265,8 +382,9 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) "mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE); memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip); - memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s, - "mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE); + memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_mailbox_ops, s, + "mchp.pfsoc.ioscb.mailbox", + MCHP_PFSOC_IOSCB_MAILBOX_SIZE); memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox); memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s, @@ -343,6 +461,8 @@ static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, const void *data) dc->desc = "Microchip PolarFire SoC IOSCB modules"; dc->realize = mchp_pfsoc_ioscb_realize; + device_class_set_legacy_reset(dc, mchp_pfsoc_ioscb_reset); + device_class_set_props(dc, mchp_pfsoc_ioscb_properties); } static const TypeInfo mchp_pfsoc_ioscb_info = { -- 2.53.0