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envelope-from=bin.meng@processmission.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Icicle Kit reference design maps the 32-bit cached and non-cached windows and both 64-bit windows to the same physical DDR from offset zero. The MSS Configurator User Guide describes configurable physical DDR offsets, so other FPGA designs can instead arrange these regions sequentially when their device trees describe that layout. QEMU models the reference design used by the tested HSS and Linux images. Treating the high windows as only the portion above 1 GiB leaves their valid memory nodes unbacked with the board's 2 GiB of DDR. Map both high windows over the full machine RAM and qualify the source comment to describe this reference-design configuration. Signed-off-by: Bin Meng Reviewed-by: Chao Liu Tested-by: Conor Dooley --- (no changes since v3) Changes in v3: - Update commit message to mention the DDR aliases is modeled following the Icicle Kit reference design hw/riscv/microchip_pfsoc.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 38f4e7d799..eea2895a0a 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -554,15 +554,29 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) TYPE_MICROCHIP_PFSOC); qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); - /* Split RAM into low and high regions using aliases to machine->ram */ + /* + * Model the Icicle Kit reference design, whose four CPU-visible windows + * alias the same physical DDR from offset zero. With 2 GiB of DDR, they + * map as follows: + * + * CPU address Attribute Visible size DDR range + * 0x0080000000 32-bit cached 1 GiB [0, 1 GiB) + * 0x00c0000000 32-bit non-cached 1 GiB [0, 1 GiB) + * 0x1000000000 64-bit cached 2 GiB [0, 2 GiB) + * 0x1400000000 64-bit non-cached 2 GiB [0, 2 GiB) + * + * "Low" and "high" describe the CPU address windows, not the lower and + * upper portions of physical DDR. Other FPGA designs can configure + * different physical offsets through the MSS segmentation registers. + */ mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size; - mem_high_size = machine->ram_size - mem_low_size; + mem_high_size = machine->ram_size; memory_region_init_alias(mem_low, NULL, "microchip.icicle.kit.ram_low", machine->ram, 0, mem_low_size); memory_region_init_alias(mem_high, NULL, "microchip.icicle.kit.ram_high", machine->ram, - mem_low_size, mem_high_size); + 0, mem_high_size); /* Register RAM */ memory_region_add_subregion(system_memory, -- 2.53.0