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envelope-from=bin.meng@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Icicle Kit has 2 GiB of RAM, and its firmware device tree describes that fixed capacity. The model currently defaults to 1537 MiB and accepts any larger size, allowing configurations that do not match the board. Set the default to 2 GiB and reject every other size. Update the documentation and L2CC qtest command line accordingly. Signed-off-by: Bin Meng Reviewed-by: Chao Liu Reviewed-by: Conor Dooley Tested-by: Conor Dooley --- (no changes since v1) docs/system/riscv/microchip-icicle-kit.rst | 4 +--- hw/riscv/microchip_pfsoc.c | 15 ++++----------- 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst index 7fdb96601a..b0ad24f174 100644 --- a/docs/system/riscv/microchip-icicle-kit.rst +++ b/docs/system/riscv/microchip-icicle-kit.rst @@ -26,9 +26,7 @@ The ``microchip-icicle-kit`` machine supports the following devices: * 2 GEM Ethernet controllers * 1 SDHC storage controller -The memory is set to 1537 MiB by default. A sanity check on RAM size is -performed in the machine init routine to prompt user to increase the RAM size -to > 1537 MiB when less than 1537 MiB RAM is detected. +The machine has a fixed 2 GiB of RAM. Other memory sizes are rejected. Boot options ------------ diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index eea2895a0a..855c719f76 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -541,10 +541,10 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) DriveInfo *dinfo = drive_get(IF_SD, 0, 0); RISCVBootInfo boot_info; - /* Sanity check on RAM size */ - if (machine->ram_size < mc->default_ram_size) { + /* The board has a fixed RAM size */ + if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); - error_report("Invalid RAM size, should be bigger than %s", sz); + error_report("Invalid RAM size, should be %s", sz); g_free(sz); exit(EXIT_FAILURE); } @@ -756,14 +756,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, mc->default_ram_id = "microchip.icicle.kit.ram"; mc->auto_create_sdcard = true; - /* - * Map 513 MiB high memory, the minimum required high memory size, because - * HSS will do memory test against the high memory address range regardless - * of physical memory installed. - * - * See memory_tests() in mss_ddr.c in the HSS source code. - */ - mc->default_ram_size = 1537 * MiB; + mc->default_ram_size = 2 * GiB; object_class_property_add(oc, "clint-timebase-frequency", "uint32_t", microchip_icicle_kit_get_clint_timebase_freq, -- 2.53.0