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envelope-from=bin.meng@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Icicle Kit contains one E51 management hart and four U54 application harts. Defaulting to two harts can accidentally boot firmware and a device tree that expect the full five-hart topology. Default to all five harts, while retaining the existing two-to-five range for users intentionally configuring fewer application harts. Document that firmware and device trees must match the selected count. Signed-off-by: Bin Meng Tested-by: Conor Dooley --- (no changes since v3) Changes in v3: - Change only the default hart count and retain the minimum of two - Document reduced topologies and matching firmware requirements docs/system/riscv/microchip-icicle-kit.rst | 3 +++ hw/riscv/microchip_pfsoc.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst index b0ad24f174..138289a913 100644 --- a/docs/system/riscv/microchip-icicle-kit.rst +++ b/docs/system/riscv/microchip-icicle-kit.rst @@ -27,6 +27,9 @@ The ``microchip-icicle-kit`` machine supports the following devices: * 1 SDHC storage controller The machine has a fixed 2 GiB of RAM. Other memory sizes are rejected. +The machine defaults to all five harts. ``-smp`` may select two to five harts, +with one E51 and one to four U54 cores. The firmware and device tree must match +the selected topology; the HSS boot flow below uses all five harts. Boot options ------------ diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 855c719f76..9d8e5916e7 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -752,7 +752,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpus = mc->min_cpus; + mc->default_cpus = mc->max_cpus; mc->default_ram_id = "microchip.icicle.kit.ram"; mc->auto_create_sdcard = true; -- 2.53.0