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Thu, 15 Oct 2026 05:56:44 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Alistair Francis , Kevin Wolf , Hanna Reitz , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: Jamin Lin , Troy Lee Subject: [PATCH v1 01/14] hw/ssi/aspeed_smc: Fix AST2700 segment end address decoding Thread-Topic: [PATCH v1 01/14] hw/ssi/aspeed_smc: Fix AST2700 segment end address decoding Thread-Index: AQHdXGn1I+GLxGB7t0ivTTYc6lEc3Q== Date: Thu, 15 Oct 2026 05:56:44 +0000 Message-ID: <20261015055642.106204-2-jamin_lin@aspeedtech.com> References: <20261015055642.106204-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261015055642.106204-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org The AST2700 Address Decoding Range Registers (SPI030 - SPI03C) define=0A= the end address as an exclusive upper bound, with a unit of 64KB:=0A= =0A= StartAdr <=3D CEx < EndAdr=0A= =0A= When the start address equals the end address, the decoding is=0A= disabled.=0A= =0A= However, aspeed_2700_smc_segment_to_reg() and=0A= aspeed_2700_smc_reg_to_segment() treat the end address as inclusive.=0A= =0A= The end offset is programmed as (addr + size - 1) and an extra 64KB is=0A= added back when decoding it. As a result, every segment is 64KB larger=0A= than the range defined by the register and overlaps the next chip=0A= select.=0A= =0A= The issue can be reproduced by booting an AST2700 ASPEED SDK image=0A= with "-d guest_errors", which reports a lot of segment overlap errors=0A= such as:=0A= =0A= aspeed_smc_flash_set_segment: new segment for CS0 is not aligned :=0A= [ 0x100000000 - 0x108010000 ]=0A= aspeed_smc_flash_overlap: new segment CS1 [ 0x108000000 - 0x110010000 ]= =0A= overlaps with CS0 [ 0x100000000 - 0x108010000 ]=0A= =0A= Fix the segment helpers to use an exclusive end address, so that the=0A= decoded segments match the definition in the AST2700 datasheet.=0A= =0A= Fixes: bdb3748dba30 ("aspeed/smc: Add AST2700 support")=0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/ssi/aspeed_smc.c | 4 ++--=0A= 1 file changed, 2 insertions(+), 2 deletions(-)=0A= =0A= diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c=0A= index bf596f7b2d..10ea9e5aa0 100644=0A= --- a/hw/ssi/aspeed_smc.c=0A= +++ b/hw/ssi/aspeed_smc.c=0A= @@ -1823,7 +1823,7 @@ static uint32_t aspeed_2700_smc_segment_to_reg(const = AspeedSMCState *s,=0A= }=0A= =0A= reg |=3D (seg->addr & AST2700_SEG_ADDR_MASK) >> 16; /* start offset */= =0A= - reg |=3D (seg->addr + seg->size - 1) & AST2700_SEG_ADDR_MASK; /* end o= ffset */=0A= + reg |=3D (seg->addr + seg->size) & AST2700_SEG_ADDR_MASK; /* end offse= t */=0A= return reg;=0A= }=0A= =0A= @@ -1836,7 +1836,7 @@ static void aspeed_2700_smc_reg_to_segment(const Aspe= edSMCState *s,=0A= =0A= if (reg) {=0A= seg->addr =3D asc->flash_window_base + start_offset;=0A= - seg->size =3D end_offset + (64 * KiB) - start_offset;=0A= + seg->size =3D end_offset - start_offset;=0A= } else {=0A= seg->addr =3D asc->flash_window_base;=0A= seg->size =3D 0;=0A= -- =0A= 2.53.0=0A=