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From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Kane Chen" <kane_chen@aspeedtech.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Kevin Wolf" <kwolf@redhat.com>,
	"Hanna Reitz" <hreitz@redhat.com>,
	"Fabiano Rosas" <farosas@suse.de>,
	"Laurent Vivier" <lvivier@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>,
	"open list:Block layer core" <qemu-block@nongnu.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>
Subject: [PATCH v1 02/14] hw/ssi/aspeed_smc: Fix AST2700 DMA flash address mask
Date: Thu, 15 Oct 2026 05:56:45 +0000	[thread overview]
Message-ID: <20261015055642.106204-3-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20261015055642.106204-1-jamin_lin@aspeedtech.com>

The DMA flash address register (SPI084) holds the offset of the
flash access within the controller's flash window. The AST2700 FMC,
SPI0 and SPI1 controllers use a dma_flash_mask of 0x2FFFFFFC, which
clears bit 28, and SPI2 uses 0x0FFFFFFC, which limits DMA to the
first 256MB of the window.

With the default segment layout, FMC CS2 is mapped at offset
0x10000000. A DMA read from that offset is masked to 0x0 and returns
data from CS0 instead of CS2.

The Linux driver programs SPI084 with the window offset masked by
0x7fffffff, so bit 28 is a valid address bit.

Set dma_flash_mask to 0x3FFFFFFC for all AST2700 controllers to cover
the full 1GB flash window.

Fixes: bdb3748dba30 ("aspeed/smc: Add AST2700 support")
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/ssi/aspeed_smc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 10ea9e5aa0..c0c3666dbc 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -1952,7 +1952,7 @@ static void aspeed_2700_fmc_class_init(ObjectClass *klass, const void *data)
     asc->features          = ASPEED_SMC_FEATURE_DMA |
                              ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |
                              ASPEED_SMC_FEATURE_DATA_FIFO;
-    asc->dma_flash_mask    = 0x2FFFFFFC;
+    asc->dma_flash_mask    = 0x3FFFFFFC;
     asc->dma_dram_mask     = 0xFFFFFFFC;
     asc->dma_start_length  = 1;
     asc->nregs             = (0x200 + (asc->cs_num_max * 0x10)) >> 2;
@@ -1989,7 +1989,7 @@ static void aspeed_2700_spi0_class_init(ObjectClass *klass, const void *data)
     asc->features          = ASPEED_SMC_FEATURE_DMA |
                              ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |
                              ASPEED_SMC_FEATURE_DATA_FIFO;
-    asc->dma_flash_mask    = 0x2FFFFFFC;
+    asc->dma_flash_mask    = 0x3FFFFFFC;
     asc->dma_dram_mask     = 0xFFFFFFFC;
     asc->dma_start_length  = 1;
     asc->nregs             = (0x200 + (asc->cs_num_max * 0x10)) >> 2;
@@ -2025,7 +2025,7 @@ static void aspeed_2700_spi1_class_init(ObjectClass *klass, const void *data)
     asc->features          = ASPEED_SMC_FEATURE_DMA |
                              ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |
                              ASPEED_SMC_FEATURE_DATA_FIFO;
-    asc->dma_flash_mask    = 0x2FFFFFFC;
+    asc->dma_flash_mask    = 0x3FFFFFFC;
     asc->dma_dram_mask     = 0xFFFFFFFC;
     asc->dma_start_length  = 1;
     asc->nregs             = (0x200 + (asc->cs_num_max * 0x10)) >> 2;
@@ -2061,7 +2061,7 @@ static void aspeed_2700_spi2_class_init(ObjectClass *klass, const void *data)
     asc->features          = ASPEED_SMC_FEATURE_DMA |
                              ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |
                              ASPEED_SMC_FEATURE_DATA_FIFO;
-    asc->dma_flash_mask    = 0x0FFFFFFC;
+    asc->dma_flash_mask    = 0x3FFFFFFC;
     asc->dma_dram_mask     = 0xFFFFFFFC;
     asc->dma_start_length  = 1;
     asc->nregs             = (0x200 + (asc->cs_num_max * 0x10)) >> 2;
-- 
2.53.0


  parent reply	other threads:[~2026-10-15  5:58 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-15  5:56 [PATCH v1 00/14] hw/arm/aspeed: Add AST1040 FMC/SPI controllers and unimplemented devices Jamin Lin
2026-10-15  5:56 ` [PATCH v1 01/14] hw/ssi/aspeed_smc: Fix AST2700 segment end address decoding Jamin Lin
2026-10-15  5:56 ` Jamin Lin [this message]
2026-10-15  5:56 ` [PATCH v1 03/14] hw/block/m25p80: Rename w25q32dw to w25q33pw Jamin Lin
2026-10-15  5:56 ` [PATCH v1 04/14] hw/block/m25p80: Add SFDP table for Winbond W25Q33PW flash Jamin Lin
2026-10-15  5:56 ` [PATCH v1 05/14] hw/misc/aspeed_scu: Correct AST1040 A0 revision ID Jamin Lin
2026-10-15  5:56 ` [PATCH v1 06/14] hw/ssi/aspeed_smc: Add AST1040 FMC and SPI controllers Jamin Lin
2026-10-15  5:56 ` [PATCH v1 07/14] hw/arm/aspeed_ast1040: Add " Jamin Lin
2026-10-15  5:56 ` [PATCH v1 08/14] hw/arm/aspeed_ast1040: Add FMC and SPI filters as unimplemented devices Jamin Lin
2026-10-15  5:56 ` [PATCH v1 09/14] hw/arm/aspeed_ast1040: Add OTP as an unimplemented device Jamin Lin
2026-10-15  5:56 ` [PATCH v1 10/14] hw/arm/aspeed_ast1040: Add Anti-Tamper Controller (ATC) " Jamin Lin
2026-10-15  5:56 ` [PATCH v1 11/14] hw/arm/aspeed_ast1040: Add I3C " Jamin Lin
2026-10-15  5:56 ` [PATCH v1 12/14] hw/arm/aspeed_ast1040: Add Caliptra " Jamin Lin
2026-10-15  5:56 ` [PATCH v1 13/14] tests/qtest/aspeed_smc: Add AST1040 SMC tests Jamin Lin
2026-10-15  5:56 ` [PATCH v1 14/14] tests/functional/arm/test_aspeed_ast1040: Update AST1040 image to aspeed-mcu-fw-hub v01.00 Jamin Lin
2026-10-15  6:20 ` [PATCH v1 00/14] hw/arm/aspeed: Add AST1040 FMC/SPI controllers and unimplemented devices Cédric Le Goater

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