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Thu, 15 Oct 2026 05:56:56 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Alistair Francis , Kevin Wolf , Hanna Reitz , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: Jamin Lin , Troy Lee Subject: [PATCH v1 07/14] hw/arm/aspeed_ast1040: Add FMC and SPI controllers Thread-Topic: [PATCH v1 07/14] hw/arm/aspeed_ast1040: Add FMC and SPI controllers Thread-Index: AQHdXGn5GhZB2LLUrEeVVWRt7kkwFQ== Date: Thu, 15 Oct 2026 05:56:51 +0000 Message-ID: <20261015055642.106204-8-jamin_lin@aspeedtech.com> References: <20261015055642.106204-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261015055642.106204-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=jamin_lin@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the FMC, SPI0 and SPI1 controllers to the AST1040 SoC. Map their=0A= register and flash memory regions, connect their interrupts, and link=0A= the DMA DRAM region to internal Hyper RAM.=0A= =0A= The AST1040 supports two SPI controllers, SPI0 and SPI1.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/arm/aspeed_ast1040.c | 38 ++++++++++++++++++++++++++++++++++++++=0A= 1 file changed, 38 insertions(+)=0A= =0A= diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c=0A= index 0b078f10c4..6e3b6900e0 100644=0A= --- a/hw/arm/aspeed_ast1040.c=0A= +++ b/hw/arm/aspeed_ast1040.c=0A= @@ -103,7 +103,9 @@ static void aspeed_soc_ast1040_init(Object *obj)=0A= Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(obj);=0A= AspeedSoCState *s =3D ASPEED_SOC(obj);=0A= AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);=0A= + char typename[64];=0A= int i;=0A= +=0A= object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);=0A= =0A= s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);= =0A= @@ -132,6 +134,13 @@ static void aspeed_soc_ast1040_init(Object *obj)=0A= object_initialize_child(obj, "wdt[*]", &s->wdt[i],=0A= "aspeed.wdt-ast2700");=0A= }=0A= +=0A= + object_initialize_child(obj, "fmc", &s->fmc, "aspeed.fmc-ast1040");=0A= +=0A= + for (i =3D 0; i < sc->spis_num; i++) {=0A= + snprintf(typename, sizeof(typename), "aspeed.spi%d-ast1040", i);= =0A= + object_initialize_child(obj, "spi[*]", &s->spi[i], typename);=0A= + }=0A= }=0A= =0A= static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)= =0A= @@ -268,6 +277,34 @@ static void aspeed_soc_ast1040_realize(DeviceState *de= v_soc, Error **errp)=0A= aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offs= et);=0A= }=0A= =0A= + /* FMC, The number of CS is set at the board level */=0A= + object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram[1]),= =0A= + &error_abort);=0A= + if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {=0A= + return;=0A= + }=0A= + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,=0A= + sc->memmap[ASPEED_DEV_FMC]);=0A= + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,=0A= + ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);=0A= + sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,=0A= + aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_FMC));=0A= +=0A= + /* SPI */=0A= + for (i =3D 0; i < sc->spis_num; i++) {=0A= + object_property_set_link(OBJECT(&s->spi[i]), "dram",=0A= + OBJECT(&s->sram[1]), &error_abort);=0A= + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {=0A= + return;=0A= + }=0A= + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,=0A= + sc->memmap[ASPEED_DEV_SPI0 + i]);=0A= + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,=0A= + ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_bas= e);=0A= + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,=0A= + aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_SPI0 += i));=0A= + }=0A= +=0A= /* Unimplemented devices */=0A= create_unimplemented_devices(OBJECT(s), s->memory, sc->unimp_devs);=0A= }=0A= @@ -292,6 +329,7 @@ static void aspeed_soc_ast1040_class_init(ObjectClass *= klass, const void *data)=0A= sc->uarts_num =3D 13;=0A= sc->sgpio_num =3D 2;=0A= sc->wdts_num =3D 8;=0A= + sc->spis_num =3D 2;=0A= sc->uarts_base =3D ASPEED_DEV_UART0;=0A= sc->irqmap =3D aspeed_soc_ast1040_irqmap;=0A= sc->memmap =3D aspeed_soc_ast1040_memmap;=0A= -- =0A= 2.53.0=0A=