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Thu, 15 Oct 2026 06:36:30 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v1 3/9] hw/misc/aspeed_scu: Add AST1080 A0 silicon revision definition Thread-Topic: [PATCH v1 3/9] hw/misc/aspeed_scu: Add AST1080 A0 silicon revision definition Thread-Index: AQHdXG+Cp+8+4plab0624wFiN0jp8Q== Date: Thu, 15 Oct 2026 06:36:29 +0000 Message-ID: <20261015063625.186708-4-jamin_lin@aspeedtech.com> References: <20261015063625.186708-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261015063625.186708-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SEZPR06MB7362:EE_|PUZPR06MB5902:EE_ x-ms-office365-filtering-correlation-id: 894d822f-e8b3-49e8-63b4-08df2a86a5e8 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add a new silicon revision constant AST1080_A0_SILICON_REV for the=0A= AST1080 SoC. This allows the SCU model and related SoC layers to=0A= identify and handle AST1080 A0 revision properly in the same way as=0A= other Aspeed SoC families.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= include/hw/misc/aspeed_scu.h | 1 +=0A= hw/misc/aspeed_scu.c | 1 +=0A= 2 files changed, 2 insertions(+)=0A= =0A= diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h=0A= index 6482038f12..a7014e43f2 100644=0A= --- a/include/hw/misc/aspeed_scu.h=0A= +++ b/include/hw/misc/aspeed_scu.h=0A= @@ -52,6 +52,7 @@ struct Aspeed2700SCUState {=0A= #define AST1030_A1_SILICON_REV 0x80010000U=0A= #define AST1060_A2_SILICON_REV 0xA0030000U=0A= #define AST1040_A0_SILICON_REV 0x80000000U=0A= +#define AST1080_A0_SILICON_REV 0xA0000100U=0A= #define AST2700_A1_SILICON_REV 0x06010103U=0A= #define AST2700_A2_SILICON_REV 0x06020103U=0A= =0A= diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c=0A= index 77f9af2ae5..df26dd0ef4 100644=0A= --- a/hw/misc/aspeed_scu.c=0A= +++ b/hw/misc/aspeed_scu.c=0A= @@ -572,6 +572,7 @@ static uint32_t aspeed_silicon_revs[] =3D {=0A= AST2700_A1_SILICON_REV,=0A= AST2700_A2_SILICON_REV,=0A= AST1040_A0_SILICON_REV,=0A= + AST1080_A0_SILICON_REV,=0A= };=0A= =0A= bool is_supported_silicon_rev(uint32_t silicon_rev)=0A= -- =0A= 2.53.0=0A=