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Thu, 15 Oct 2026 06:36:32 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v1 4/9] hw/arm/aspeed_ast1040: Add AST1080 SoC support Thread-Topic: [PATCH v1 4/9] hw/arm/aspeed_ast1040: Add AST1080 SoC support Thread-Index: AQHdXG+DjCguOhKjGk2HEKtC83yx8w== Date: Thu, 15 Oct 2026 06:36:30 +0000 Message-ID: <20261015063625.186708-5-jamin_lin@aspeedtech.com> References: <20261015063625.186708-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261015063625.186708-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SEZPR06MB7362:EE_|KUZPR06MB8944:EE_ x-ms-office365-filtering-correlation-id: 802d034b-d4a9-4829-bee2-08df2a86a710 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add initial support for the Aspeed AST1080 SoC. The AST1080 reuses most=0A= of the AST1040 peripheral device models, as the two SoCs share nearly=0A= the same controllers including WDT, SCU, GPIO, SGPIO, ADC, I2C, FMC,=0A= and SPI.=0A= =0A= The common initialization and realization functions,=0A= aspeed_soc_ast10x0_g2_init() and aspeed_soc_ast10x0_g2_realize(),=0A= introduced in the previous patches are reused, so AST1080 can=0A= instantiate the existing AST1040 device models without defining=0A= duplicate device types.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/arm/aspeed_ast1040.c | 47 +++++++++++++++++++++++++++++++++++++++++=0A= 1 file changed, 47 insertions(+)=0A= =0A= diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c=0A= index 28abbe7010..c641f84fbe 100644=0A= --- a/hw/arm/aspeed_ast1040.c=0A= +++ b/hw/arm/aspeed_ast1040.c=0A= @@ -162,6 +162,11 @@ static void aspeed_soc_ast1040_init(Object *obj)=0A= object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);=0A= }=0A= =0A= +static void aspeed_soc_ast1080_init(Object *obj)=0A= +{=0A= + aspeed_soc_ast10x0_g2_init(obj);=0A= +}=0A= +=0A= static bool aspeed_soc_ast10x0_g2_realize(Aspeed10x0SoCState *a, Error **e= rrp)=0A= {=0A= AspeedSoCState *s =3D ASPEED_SOC(a);=0A= @@ -342,6 +347,15 @@ static void aspeed_soc_ast1040_realize(DeviceState *de= v_soc, Error **errp)=0A= aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_PECI));=0A= }=0A= =0A= +static void aspeed_soc_ast1080_realize(DeviceState *dev_soc, Error **errp)= =0A= +{=0A= + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc);=0A= +=0A= + if (!aspeed_soc_ast10x0_g2_realize(a, errp)) {=0A= + return;=0A= + }=0A= +}=0A= +=0A= static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *= data)=0A= {=0A= static const char * const valid_cpu_types[] =3D {=0A= @@ -370,12 +384,45 @@ static void aspeed_soc_ast1040_class_init(ObjectClass= *klass, const void *data)=0A= sc->num_cpus =3D 1;=0A= }=0A= =0A= +static void aspeed_soc_ast1080_class_init(ObjectClass *klass, const void *= data)=0A= +{=0A= + static const char * const valid_cpu_types[] =3D {=0A= + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */=0A= + NULL=0A= + };=0A= + DeviceClass *dc =3D DEVICE_CLASS(klass);=0A= + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc);=0A= +=0A= + /* Reason: The Aspeed SoC can only be instantiated from a board */=0A= + dc->user_creatable =3D false;=0A= + dc->realize =3D aspeed_soc_ast1080_realize;=0A= +=0A= + sc->valid_cpu_types =3D valid_cpu_types;=0A= + sc->silicon_rev =3D AST1080_A0_SILICON_REV;=0A= + sc->sram_size[0] =3D 128 * KiB;=0A= + sc->sram_size[1] =3D 16 * MiB; /* Hyper RAM */=0A= + sc->uarts_num =3D 13;=0A= + sc->sgpio_num =3D 1;=0A= + sc->wdts_num =3D 8;=0A= + sc->spis_num =3D 2;=0A= + sc->uarts_base =3D ASPEED_DEV_UART0;=0A= + sc->irqmap =3D aspeed_soc_ast1040_irqmap;=0A= + sc->memmap =3D aspeed_soc_ast1040_memmap;=0A= + sc->num_cpus =3D 1;=0A= +}=0A= +=0A= static const TypeInfo aspeed_soc_ast1040_types[] =3D {=0A= {=0A= .name =3D "ast1040-a0",=0A= .parent =3D TYPE_ASPEED10X0_SOC,=0A= .instance_init =3D aspeed_soc_ast1040_init,=0A= .class_init =3D aspeed_soc_ast1040_class_init,=0A= + },=0A= + {=0A= + .name =3D "ast1080-a0",=0A= + .parent =3D TYPE_ASPEED10X0_SOC,=0A= + .instance_init =3D aspeed_soc_ast1080_init,=0A= + .class_init =3D aspeed_soc_ast1080_class_init,=0A= }=0A= };=0A= =0A= -- =0A= 2.53.0=0A=