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Tsirkin" To: David Vrabel Cc: "qemu-devel@nongnu.org" , Zhao Liu , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Paolo Bonzini , Pierrick Bouvier Subject: Re: [PATCH v3 0/4] hw/pci-bridge: Configurable apparent bandwidth for the PCIe topology Message-ID: <20261015101016-mutt-send-email-mst@kernel.org> References: <20260928152431.310363-1-david.vrabel@nutanix.com> <6fa1a07f-afbb-4c65-85e0-ddcebd9bddec@nutanix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6fa1a07f-afbb-4c65-85e0-ddcebd9bddec@nutanix.com> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Oct 15, 2026 at 02:41:55PM +0100, David Vrabel wrote: > > ping? > On 28/09/2026 16:24, David Vrabel wrote: > > When a VM has been assigned a number of PCIe devices behind a common > > PCIe switch and the VM intends to use peer-to-peer (P2P) transfers > > between the devices, it is useful to be able to more report the > > apparent PCIe bandwidth so it reflects the real handwidth of the > > underlying hardware. This allows software in the VM (such as NCCL[1]) > > to make better decisions about whether to use P2P or not. > > > > The existing emulated PCIe switch is a vintage TI XIO3130 and only > > support 2.5 GT/s and x1, so we introduces new generic upstream and > > downstream port devices (pcie-upstream-port and pcie-downstream-port), > > inspired by the existing generic pcie-root-port device. > > > > The existing experimental "x-speed" and "x-width" options are made > > non-experimental, allowing the pcie-root-port and pcie-downstream-port > > capabilities to be configured to match the hardware. > > > > The pcie-root-port device is updated to default to a Gen6 capable > > device. > > > > Finally, where a root or upstream port's bandwidth has been limited, > > we also ensure the other end of the link reports the same link status. will merge, thanks!