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[35.194.223.33]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cd654a249f3sm437294a12.27.2026.10.15.21.02.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 21:02:32 -0700 (PDT) From: Kuan-Wei Chiu To: trini@konsulko.com, ilias.apalodimas@linaro.org Cc: marscheng@google.com, eleanor15x@gmail.com, jserv@ccns.ncku.edu.tw, u-boot@lists.u-boot-project.org, Kuan-Wei Chiu Subject: [PATCH 2/4] board: google: Add Google Tensor G5 board support Date: Fri, 16 Oct 2026 04:02:14 +0000 Message-ID: <20261016040216.3636305-3-visitorckw@gmail.com> X-Mailer: git-send-email 2.56.0.212.g129ede20d9-goog In-Reply-To: <20261016040216.3636305-1-visitorckw@gmail.com> References: <20261016040216.3636305-1-visitorckw@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Add initial board support for Google Tensor G5 SoC boards. U-Boot runs as BL33 loaded at 0xbe000000. Configure the MMU map, DRAM bounds, and disable the APC watchdog left running by earlier bootloader stages. Signed-off-by: Kuan-Wei Chiu --- MAINTAINERS | 2 ++ arch/arm/mach-google/Kconfig | 11 ++++++ board/google/lga/Kconfig | 14 ++++++++ board/google/lga/MAINTAINERS | 5 +++ board/google/lga/Makefile | 3 ++ board/google/lga/lga.c | 65 ++++++++++++++++++++++++++++++++++++ include/configs/lga.h | 9 +++++ 7 files changed, 109 insertions(+) create mode 100644 board/google/lga/Kconfig create mode 100644 board/google/lga/MAINTAINERS create mode 100644 board/google/lga/Makefile create mode 100644 board/google/lga/lga.c create mode 100644 include/configs/lga.h diff --git a/MAINTAINERS b/MAINTAINERS index 36b4c7f0246..2d8ffe7887a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -360,6 +360,8 @@ ARM GOOGLE TENSOR SOC SUPPORT M: Kuan-Wei Chiu S: Maintained F: arch/arm/mach-google/ +F: board/google/lga/ +F: include/configs/lga.h K: [gG]oogle.?[tT]ensor ARM HISILICON diff --git a/arch/arm/mach-google/Kconfig b/arch/arm/mach-google/Kconfig index a9e605ebb82..f6a5c9c43f2 100644 --- a/arch/arm/mach-google/Kconfig +++ b/arch/arm/mach-google/Kconfig @@ -1,7 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later if ARCH_GOOGLE config SYS_VENDOR default "google" +config TARGET_GOOGLE_LGA + bool "Google Tensor G5 (LGA)" + default y + help + Support for Google Tensor G5 (Laguna) SoC and boards based on it, + including Frankel (Pixel 10), Blazer (Pixel 10 Pro), and Mustang + (Pixel 10 Pro XL). + +source "board/google/lga/Kconfig" + endif diff --git a/board/google/lga/Kconfig b/board/google/lga/Kconfig new file mode 100644 index 00000000000..22bb233f140 --- /dev/null +++ b/board/google/lga/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if TARGET_GOOGLE_LGA + +config SYS_BOARD + default "lga" + +config SYS_SOC + default "lga" + +config SYS_CONFIG_NAME + default "lga" + +endif diff --git a/board/google/lga/MAINTAINERS b/board/google/lga/MAINTAINERS new file mode 100644 index 00000000000..1dd03afab42 --- /dev/null +++ b/board/google/lga/MAINTAINERS @@ -0,0 +1,5 @@ +GOOGLE TENSOR G5 (LGA) BOARD +M: Kuan-Wei Chiu +S: Maintained +F: board/google/lga/ +F: include/configs/lga.h diff --git a/board/google/lga/Makefile b/board/google/lga/Makefile new file mode 100644 index 00000000000..4343e05c78f --- /dev/null +++ b/board/google/lga/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-y += lga.o diff --git a/board/google/lga/lga.c b/board/google/lga/lga.c new file mode 100644 index 00000000000..e495d34ce0b --- /dev/null +++ b/board/google/lga/lga.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2026 Google LLC + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define LGA_WDT1_BASE 0x200c5000 +#define LGA_WDT_CONTROL 0x08 +#define LGA_WDT_CONTROL_ENABLE BIT(0) +#define LGA_WDT_KEY 0x10 +#define LGA_WDT_KEY_UNLOCK 0x00c0ffee + +#define LGA_SDRAM_BASE 0x80000000UL +#define LGA_SDRAM_SIZE 0x80000000UL +#define LGA_BL33_RAM_TOP 0xc0000000UL + +static struct mm_region lga_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + .virt = LGA_SDRAM_BASE, + .phys = LGA_SDRAM_BASE, + .size = LGA_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + 0, + } +}; + +struct mm_region *mem_map = lga_mem_map; + +int dram_init(void) +{ + gd->ram_base = LGA_SDRAM_BASE; + gd->ram_size = LGA_SDRAM_SIZE; + + return 0; +} + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + return LGA_BL33_RAM_TOP; +} + +int board_init(void) +{ + writel(LGA_WDT_KEY_UNLOCK, LGA_WDT1_BASE + LGA_WDT_KEY); + clrbits_le32(LGA_WDT1_BASE + LGA_WDT_CONTROL, LGA_WDT_CONTROL_ENABLE); + writel(0, LGA_WDT1_BASE + LGA_WDT_KEY); + + return 0; +} diff --git a/include/configs/lga.h b/include/configs/lga.h new file mode 100644 index 00000000000..c770c5837f4 --- /dev/null +++ b/include/configs/lga.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2026 Google LLC + */ + +#ifndef __CONFIG_LGA_H +#define __CONFIG_LGA_H + +#endif /* __CONFIG_LGA_H */ -- 2.56.0.212.g129ede20d9-goog