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Fri, 16 Oct 2026 02:17:06 -0700 (PDT) From: Pablo Mazzini To: Andre Przywara , u-boot@lists.u-boot-project.org Cc: Tom Rini , linux-sunxi@lists.linux.dev, Lukasz Majewski Subject: [PATCH 4/7] clk: sunxi: add the Allwinner B288 gates and resets Date: Fri, 16 Oct 2026 10:16:05 +0100 Message-ID: <20261016091608.121842-5-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261016091608.121842-1-pmazzini@gmail.com> References: <20261016091608.121842-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The bus clock gates and resets, as in the Linux CCU driver. Signed-off-by: Pablo Mazzini --- drivers/clk/sunxi/Kconfig | 7 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_b288.c | 101 ++++++++++++++++++++++++++++++++++ drivers/clk/sunxi/clk_sunxi.c | 5 ++ 4 files changed, 114 insertions(+) create mode 100644 drivers/clk/sunxi/clk_b288.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 1c1cc82719c..e4fe6f63626 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -52,6 +52,13 @@ config CLK_SUN8I_A23 This enables common clock driver support for platforms based on Allwinner A23/A33 SoC. +config CLK_SUN8I_B288 + bool "Clock driver for Allwinner B288" + default MACH_SUN8I_B288 + help + This enables common clock driver support for platforms based + on Allwinner B288 SoC. + config CLK_SUN8I_A83T bool "Clock driver for Allwinner A83T" default MACH_SUN8I_A83T diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 93b542cebcd..4f278ff551a 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o +obj-$(CONFIG_CLK_SUN8I_B288) += clk_b288.o obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o diff --git a/drivers/clk/sunxi/clk_b288.c b/drivers/clk/sunxi/clk_b288.c new file mode 100644 index 00000000000..505fa27f83a --- /dev/null +++ b/drivers/clk/sunxi/clk_b288.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Allwinner B288 (sun8iw10p1) CCU gates and resets + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct ccu_clk_gate b288_gates[] = { + [CLK_BUS_DMA] = GATE(0x060, BIT(6)), + [CLK_BUS_SDMMC0_BUS] = GATE(0x060, BIT(8)), + [CLK_BUS_SDMMC1_BUS] = GATE(0x060, BIT(9)), + [CLK_BUS_SDMMC2_BUS] = GATE(0x060, BIT(10)), + [CLK_BUS_SDMMC3_BUS] = GATE(0x060, BIT(11)), + [CLK_BUS_NAND] = GATE(0x060, BIT(13)), + [CLK_BUS_SDRAM] = GATE(0x060, BIT(14)), + [CLK_BUS_PSRAM] = GATE(0x060, BIT(15)), + [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), + [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), + [CLK_BUS_SPI2] = GATE(0x060, BIT(22)), + [CLK_BUS_USBOTG] = GATE(0x060, BIT(24)), + [CLK_BUS_USBEHCI0] = GATE(0x060, BIT(26)), + [CLK_BUS_USBOHCI0] = GATE(0x060, BIT(29)), + [CLK_BUS_TCON0] = GATE(0x064, BIT(4)), + [CLK_BUS_CSI] = GATE(0x064, BIT(8)), + [CLK_BUS_DE] = GATE(0x064, BIT(12)), + [CLK_BUS_EE] = GATE(0x064, BIT(13)), + [CLK_BUS_ADDA] = GATE(0x068, BIT(0)), + [CLK_BUS_SPDIF] = GATE(0x068, BIT(1)), + [CLK_BUS_DSD] = GATE(0x068, BIT(2)), + [CLK_BUS_DMIC] = GATE(0x068, BIT(3)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), + [CLK_BUS_THS] = GATE(0x068, BIT(8)), + [CLK_BUS_KEYADC] = GATE(0x068, BIT(9)), + [CLK_BUS_GPADC] = GATE(0x068, BIT(10)), + [CLK_BUS_I2S0] = GATE(0x068, BIT(12)), + [CLK_BUS_I2S1] = GATE(0x068, BIT(13)), + [CLK_BUS_TWI0] = GATE(0x06c, BIT(0)), + [CLK_BUS_TWI1] = GATE(0x06c, BIT(1)), + [CLK_BUS_TWI2] = GATE(0x06c, BIT(2)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), + [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), + [CLK_BUS_UART5] = GATE(0x06c, BIT(21)), +}; + +static const struct ccu_reset b288_resets[] = { + [RST_USBPHY0] = RESET(0x0cc, BIT(0)), + [RST_MBUS] = RESET(0x0fc, BIT(31)), + [RST_BUS_DMA] = RESET(0x2c0, BIT(6)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)), + [RST_BUS_NAND] = RESET(0x2c0, BIT(13)), + [RST_BUS_DRAM] = RESET(0x2c0, BIT(14)), + [RST_BUS_PSRAM] = RESET(0x2c0, BIT(15)), + [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), + [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), + [RST_BUS_SPI2] = RESET(0x2c0, BIT(22)), + [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), + [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), + [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)), + [RST_BUS_WLAN] = RESET(0x2c4, BIT(1)), + [RST_BUS_TCON0] = RESET(0x2c4, BIT(4)), + [RST_BUS_CSI] = RESET(0x2c4, BIT(8)), + [RST_BUS_DE] = RESET(0x2c4, BIT(12)), + [RST_BUS_EE] = RESET(0x2c4, BIT(13)), + [RST_BUS_ADDA] = RESET(0x2d0, BIT(0)), + [RST_BUS_SPDIF] = RESET(0x2d0, BIT(1)), + [RST_BUS_DSD] = RESET(0x2d0, BIT(2)), + [RST_BUS_DMIC] = RESET(0x2d0, BIT(3)), + [RST_BUS_THS] = RESET(0x2d0, BIT(8)), + [RST_BUS_KEYADC] = RESET(0x2d0, BIT(9)), + [RST_BUS_GPADC] = RESET(0x2d0, BIT(10)), + [RST_BUS_I2S0] = RESET(0x2d0, BIT(12)), + [RST_BUS_I2S1] = RESET(0x2d0, BIT(13)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), + [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), + [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), + [RST_BUS_UART3] = RESET(0x2d8, BIT(19)), + [RST_BUS_UART4] = RESET(0x2d8, BIT(20)), + [RST_BUS_UART5] = RESET(0x2d8, BIT(21)), +}; + +const struct ccu_desc b288_ccu_desc = { + .gates = b288_gates, + .resets = b288_resets, + .num_gates = ARRAY_SIZE(b288_gates), + .num_resets = ARRAY_SIZE(b288_resets), +}; diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 046d5d1605a..5f40f30fe89 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -117,6 +117,7 @@ extern const struct ccu_desc a64_ccu_desc; extern const struct ccu_desc a80_ccu_desc; extern const struct ccu_desc a80_mmc_clk_desc; extern const struct ccu_desc a83t_ccu_desc; +extern const struct ccu_desc b288_ccu_desc; extern const struct ccu_desc d1_ccu_desc; extern const struct ccu_desc f1c100s_ccu_desc; extern const struct ccu_desc h3_ccu_desc; @@ -154,6 +155,10 @@ static const struct udevice_id sunxi_clk_ids[] = { { .compatible = "allwinner,sun8i-a33-ccu", .data = (ulong)&a23_ccu_desc }, #endif +#ifdef CONFIG_CLK_SUN8I_B288 + { .compatible = "allwinner,sun8i-b288-ccu", + .data = (ulong)&b288_ccu_desc }, +#endif #ifdef CONFIG_CLK_SUN8I_A83T { .compatible = "allwinner,sun8i-a83t-ccu", .data = (ulong)&a83t_ccu_desc }, -- 2.52.0