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Fri, 16 Oct 2026 02:17:10 -0700 (PDT) From: Pablo Mazzini To: Andre Przywara , u-boot@lists.u-boot-project.org Cc: Tom Rini , linux-sunxi@lists.linux.dev, Peng Fan , Tanmay Kathpalia , Jaehoon Chung Subject: [PATCH 6/7] mmc: sunxi: B288 mmc0/mmc1 run off PLL_PERIPH0 2x Date: Fri, 16 Oct 2026 10:16:07 +0100 Message-ID: <20261016091608.121842-7-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261016091608.121842-1-pmazzini@gmail.com> References: <20261016091608.121842-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Their mux input 1 is PLL_PERIPH0 2x, and unlike mmc2/mmc3 they do not halve it. Signed-off-by: Pablo Mazzini --- drivers/mmc/sunxi_mmc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 84f4e4c2198..7329ca3e24e 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -100,6 +100,13 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) pll_hz /= 2; + /* + * The B288's mux input 1 is PLL_PERIPH0 2x, and only the + * mmc2/mmc3 controllers halve it. + */ + if (IS_ENABLED(CONFIG_MACH_SUN8I_B288) && priv->mmc_no < 2) + pll_hz *= 2; + /* * The A523/T527 uses PERIPH0_400M as the MMC0/1 input clock, * and PERIPH0_800M for MMC2. There is also the hidden divider -- 2.52.0