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Fri, 16 Oct 2026 06:25:20 -0700 Received: from build-va-bionic-20260204.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Fri, 16 Oct 2026 06:25:20 -0700 From: Vishwaroop A To: Thierry Reding , Jonathan Hunter , Mark Brown CC: Sowjanya Komatineni , Laxman Dewangan , Breno Leitao , Aaron Kling , Carol Soto , Suresh Mangipudi , Vishwaroop A , , , Subject: [PATCH 0/2] spi: tegra210-quad: Fix timeout path status handling and DMA leak Date: Fri, 16 Oct 2026 13:25:18 +0000 Message-ID: <20261016132520.3723412-1-va@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF000264B2:EE_|CHBPR12MB319464:EE_ X-MS-Office365-Filtering-Correlation-Id: ddbdec53-f5c2-43a7-9405-08df2b88fe3f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|36860700016|82310400026|56012099006|11063799006|261009223027099003|10067099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xiSx/jKy7/Jde6wzeskOtAQYz6OkmcaEjlJR4/gOxWzyAvmKyjlKMde4CENpXIfBOC+F4Ly/3HzQI9wc9GOm3FbmGlfadozpoSHqdSItY+xo0eV2xSxgZYws7zRZAHAlzIgE/vy7H1lb9uQ5QrpkmxhEyBFiMppYktiSPoa9YhQmxrHBHgOjqT+Rb0Rpe/UChmRIsmu+TldbdtUJONvf2qH2YWYFNo6UC5551SRCkYAOLS1tZZSyeYFd/1scpQwHN6Sn9QbRW5BuN6OWcOw2crFYpPa+OPintArPwDR8BJz6Db6f4PvlJN1jUnNpXWxyCYjM4DS25CN5cd1YccmJgvhIcvOavwhvmJoUTuacdxyO4Q95jtf+dboi47qQeqmzvc5/75kSCL9ORbGxjkfwr8RK2OW2NTFte6SupqMCT3oxnJ2Qjd7BHjso5AQiGdzE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 13:25:49.0588 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddbdec53-f5c2-43a7-9405-08df2b88fe3f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF000264B2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CHBPR12MB319464 Two independent fixes in the Tegra QSPI transfer timeout path. Patch 1 fixes a regression from commit 1ff82c13ea94 ("spi: tegra210-quad: Cache TRANS_STATUS in ISR for timeout handler"), currently in linux-next only. When tegra_qspi_handle_timeout() observes a real ISR completion after draining the workqueue, it still publishes the pre-drain lost-IRQ FIFO snapshot. That snapshot can hold zeroed error bits if the ISR W1C-ed the hardware between the two reads, which makes the manual completion handler downstream accept a transfer that actually reported a FIFO underflow or overflow. No stable backport is needed because the offending commit has not been released. Patch 2 fixes a DMA mapping leak present since the driver was added. tegra_qspi_dma_map_xfer() maps the client TX/RX buffers, but the only unmap lives in handle_dma_based_xfer(), which runs from the interrupt bottom half. On a genuine timeout the bottom half never runs and both transfer paths abort with tegra_qspi_dma_stop() plus a controller reset without unmapping, so every real timeout leaks the streaming mappings for that chunk. On systems with an IOMMU in front of QSPI this gradually exhausts the IOVA space. This one is tagged for stable. Both issues surfaced while reviewing a downstream backport of the hard-IRQ series now in linux-next; patch 1 carries the corresponding Reported-by and Link tags. Vishwaroop A (2): spi: tegra210-quad: don't overwrite refreshed status with lost-IRQ snapshot spi: tegra210-quad: Unmap DMA buffers on transfer timeout drivers/spi/spi-tegra210-quad.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) -- 2.17.1