From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EC983A900B; Sat, 17 Oct 2026 16:30:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792254636; cv=none; b=WbHBxOOuGY8hUEI4CChxqCo/WKk59nSEE85evygcdpSB6gjjjIYDjpYhlPgQMfmf2qoOJzb9bzaoIM0U0lsywDI9cxHGz8Y2YHsRL6FyV7ZTVrv+7zPYRLw7xtLbsOcKBiNBYwDlGZIx8yj639IvD6X/0GuKLKJpN/L2Xzi0WJE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792254636; c=relaxed/simple; bh=1gjMEjtCHHhZgh7Ol1yK839ioeGgwHyOwdNY7roglW8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=akFMq1J6jdvPo8sx8matwOW0BiFtyVQSnAKkg2UVAhDxtc/EBayiNs2M+1sG2q2IVI7Iyn1PTG/8H4nMzABS8dXNR5A7wHeHPrERgL0wnEBmLdUciDkmeXU3fllv/R5rEXSLbc6Pz+k7q/oXovE5vIcBQpjzIQ1Qnjf7I6hRoRI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=Dx6B1ppq; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="Dx6B1ppq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E836D1F000C5; Sat, 17 Oct 2026 16:30:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1792254634; bh=aQy2Ch4iSXMj/3Hq8zkXqGH5H/WQx3cDdzxRt/1OIng=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Dx6B1ppqm8DIrgSz2DYkxOUZtx/fsTW9NvON9kYhL6ejOkS6xhrhf9rE+dF6Gq4OH cqNvg9Tz1DamNP4/GRZN1J5UGlgflo2r0XAFega4OjT6fpTdM+ErU42wTVzpdE0A28 Hi0oLUOHZP+WiC9LO4C+c9y1ws4udAMUqk2ELnyM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Pavan Chebbi , Kalesh AP , Michael Chan , Jakub Kicinski , Sasha Levin Subject: [PATCH 6.12 510/869] bnxt_en: Disable EOP for TPA on all chips to prevent data corruption Date: Sat, 17 Oct 2026 17:55:51 +0200 Message-ID: <20261017160050.177313081@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261017160036.979869304@linuxfoundation.org> References: <20261017160036.979869304@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Michael Chan [ Upstream commit c3faf548a00f4c17100cc9204746975fa46a73b9 ] EOP (End of frame padding) on the AGG ring may cause overlapping of zero padding at the end of one segment with the next segment's data. If Relaxed Ordering (RO) is enabled, the zero padding may overwrite valid data in the next segment and corrupt the data. Older chips (P5 and older) do not automatically disable RO when EOP is enabled. On some ARM systems, data corruption was reported on 57508 (P5) chips with RO enabled. Always disable EOP on all chips on the AGG rings when TPA is enabled to fix the data corruption. Fixes: bfcd8d791ec1 ("bnxt_en: Add fast path logic for TPA on 57500 chips.") Reviewed-by: Pavan Chebbi Reviewed-by: Kalesh AP Signed-off-by: Michael Chan Link: https://patch.msgid.link/20260731190937.807270-5-michael.chan@broadcom.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index 497799b089ce2..dc2bc7a2de0e3 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -4311,11 +4311,14 @@ static void bnxt_init_one_rx_agg_ring_rxbd(struct bnxt *bp, type = ((u32)rxr->rx_page_size << RX_BD_LEN_SHIFT) | RX_BD_TYPE_RX_AGG_BD; - /* On P7, setting EOP will cause the chip to disable - * Relaxed Ordering (RO) for TPA data. Disable EOP for - * potentially higher performance with RO. + /* Disable EOP if TPA is enabled to prevent overlapping zero + * padding with the next segment's data. On P7_PLUS, EOP will + * automatically disable Relaxed Ordering (RO) to prevent + * potential data corruption (and may degrade performance). On + * older chips, RO will not be automatically disabled and may + * cause corruption. */ - if (BNXT_CHIP_P5_AND_MINUS(bp) || !(bp->flags & BNXT_FLAG_TPA)) + if (!(bp->flags & BNXT_FLAG_TPA)) type |= RX_BD_FLAGS_AGG_EOP; bnxt_init_rxbd_pages(ring, type); -- 2.53.0