From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D67CC3BB9E1; Sat, 17 Oct 2026 17:15:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792257341; cv=none; b=kSgCbFrrTeCMv/AtsHfRnxszRmjfUwuJeaMsrwHZtLYQYHipy9CcZLp6USqENucCQLgqTEsFL8uhEwzIF3Ky856ZfYL7QNsxyjZAqEI4KVtgcMRfBl36IyBxkKmk1Zy4hGWRSZocBfRYZyAh4+ye6i3kdg12CHFU5ljqx5sD7ns= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792257341; c=relaxed/simple; bh=MP29x1je6eL0oJDXJUSddE884vCgpRm/GnsiCBndslU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kdmm0U/NEtQbn7tUqQP/pqaBQwHcNTD0G1rAYgSvrn8SdHsB326fXAN89jtbmDfKeduJfx1staVDhjF39cXrYvBCN2z92ZhJjIu0NEX+KsfUS1K8jp6i0zD2iAFhM5qGq7zvcVwWEAOSNXGFRegYrSQrrUHHGweUqXdkFiJFsms= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=dDuZLIgy; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="dDuZLIgy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DCBE61F000C4; Sat, 17 Oct 2026 17:15:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1792257339; bh=dxhvgExzO/0jBcuIGhlhSfZyyWdXsJD8GtIuvz5SKDI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dDuZLIgyZdBM6knZJ7CyhjEL75NAPkuGrgUEnWdZ/8hnXySayI8cJgqy05Zm1vfWw BRFqYTeLbv4obGkrGe5/BlaS/Jx+SeArzun3jLPK/OmKR/H1KV3EqoYKdadaL5a4Sp OO/MezzugOypN2SK/2D4wAzeEy0Y3EzQPhVPMdwY= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Yazen Ghannam , Vishal Badole , "Borislav Petkov (AMD)" Subject: [PATCH 6.6 0486/1674] EDAC/amd64: Mask UMC chip select to the four implemented selects Date: Sat, 17 Oct 2026 17:45:58 +0200 Message-ID: <20261017160443.589987271@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261017160431.119607952@linuxfoundation.org> References: <20261017160431.119607952@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Vishal Badole commit 7484bc43ba6b8e189b482db5b75e7842890a82b1 upstream. For DRAM ECC errors, the chip select value can be found in the MCA_SYND[ErrorInformation] field. ErrorInformation[2:0] was first documented in Zen1. The 3 bit field implied that up to 8 chip selects may be used. However, all Zen-based systems have only ever had up to 4 chip selects. So only bits [1:0] would contain a valid chip select value. Future systems are redefining the field to ErrorInformation[1:0]. This matches the existing 'up to 4 chip selects' implementations. And it frees up the extra bit for other decoding. Change the current chip select mask from 0x7 to 0x3 to prepare for the decode change. Fixes: 713ad54675fd ("EDAC, amd64: Define and register UMC error decode function") Suggested-by: Yazen Ghannam Signed-off-by: Vishal Badole Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Yazen Ghannam Cc: Link: https://patch.msgid.link/20261002113204.3358815-2-Vishal.Badole@amd.com Signed-off-by: Greg Kroah-Hartman --- drivers/edac/amd64_edac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3068,13 +3068,13 @@ static inline void decode_bus_error(int * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel * number. * - * For DRAM ECC errors, the Chip Select number is given in bits [2:0] of + * For DRAM ECC errors, the Chip Select number is given in bits [1:0] of * the MCA_SYND[ErrorInformation] field. */ static void umc_get_err_info(struct mce *m, struct err_info *err) { err->channel = (m->ipid & GENMASK(31, 0)) >> 20; - err->csrow = m->synd & 0x7; + err->csrow = m->synd & 0x3; } static void decode_umc_error(int node_id, struct mce *m)