From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C53F23AE198; Sat, 17 Oct 2026 17:16:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792257368; cv=none; b=YBHADUBTS6xBHaU4QUIIy4U/dV4rtWYQg05ekbzLIxeUx9az5ko9JxiNzOq8nAQsduHw367kX8Srkw6mdLcWXGqaAOsy1YNLp8JSh+o73bzOkONWF7kN/Ryz4AxYQSRFtL4uiuE8swW33vjhoxD2K+eqhQhMckfW6Se8ZXvoy0U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792257368; c=relaxed/simple; bh=nXC/Ayx3RBNOWWNZqymkf80mRFMfqwCRx+V1GCbyJ6s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sihYRnMahlGYtBfRlCo3Ouoea1NlSI4tjn/BJrOKyFQR4Ot2TGLLda/rihYek4iSJLE0K6KaqIYTmoIctbroph6PoELkU3c3i3VlrAf0tkAmntrloAhcaa0oKP08LsNExVarpjkQxWPWcYCzOQd7WVVLK5+fmAQb7/5cdE5/A98= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=U8fE9dtT; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="U8fE9dtT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2020C1F000C4; Sat, 17 Oct 2026 17:16:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1792257367; bh=rXyPTf9sA7REI8RSuQOwl6bMI3cUKtdLal6m4OM/uy8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=U8fE9dtTh0KhZIzuIZv/6OkwtKgMc6wYKCANpetLB9HCqI+2nule2PbS0A65W+48P EGuEOd4VZSJKrsQo1Mcr85GsE5TK/8XC1PZ2hGR8p0Kai0msDkUem9IPhS47tJY3K4 EB1cVJzKR4gx3xju6Dth20hoVd1hE60UrvYmNClU= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Ijae Kim , Myeonghun Pak , Thomas Zimmermann , Sasha Levin Subject: [PATCH 6.6 0538/1674] drm/aspeed: Balance the display clock enable on teardown Date: Sat, 17 Oct 2026 17:46:50 +0200 Message-ID: <20261017160444.912500606@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261017160431.119607952@linuxfoundation.org> References: <20261017160431.119607952@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Myeonghun Pak [ Upstream commit ecce445c6489895463b7ddec2af66338287fee4c ] aspeed_gfx_load() enables the display clock without checking the return value and never disables it on probe failure or removal. devm_clk_get() only releases the clock reference, leaving the enable unbalanced. Use devm_clk_get_enabled() to handle enable failures and automatically disable and unprepare the clock on probe failure or removal. This issue was identified during our ongoing static-analysis research while reviewing kernel code. Fixes: 4f2a8f5898ec ("drm: Add ASPEED GFX driver") Co-developed-by: Ijae Kim Signed-off-by: Ijae Kim Signed-off-by: Myeonghun Pak Assisted-by: OpenAI:GPT-5.6 Reviewed-by: Thomas Zimmermann Signed-off-by: Thomas Zimmermann Link: https://patch.msgid.link/20260913223019.89651-1-mhun512@gmail.com Link: https://patch.msgid.link/20260905080426.34224-1-kmehltretter@gmail.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c index 78122b35a0cbb..68d425f8e2a3d 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c @@ -193,13 +193,12 @@ static int aspeed_gfx_load(struct drm_device *drm) } reset_control_deassert(priv->rst); - priv->clk = devm_clk_get(drm->dev, NULL); + priv->clk = devm_clk_get_enabled(drm->dev, NULL); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, - "missing or invalid clk device tree entry"); + "failed to get and enable clock\n"); return PTR_ERR(priv->clk); } - clk_prepare_enable(priv->clk); /* Sanitize control registers */ writel(0, priv->base + CRT_CTRL1); -- 2.53.0