From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72FD735E93B; Sat, 17 Oct 2026 17:32:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792258351; cv=none; b=tHtqZ+ZS5zLCvmh+X5tzT8CW+uhAfpr0ns8vyDeODiNMvlwsMPo5Rpv6U6ZkxX4M8tG9xhHAGbGYBt1+pfsWTzlsMkm2eDiDlmQ0DhPemP9qrzvtGiTtYQ7sCDESCOyByCFliia3ybGVF00SvcG/39x9Qk+bpR3lFjpWW0mgUDA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792258351; c=relaxed/simple; bh=y74ztpvA3M/GtXETmrDtAXLNTyUGCmVpFWU2pWWtWS0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k8oFFeAK36pqiozZrzm7Zit2Ron5k1wnpSoDL1+d3fLrL5RPMJqVMTTOfTMJxxhmoP+iyMLh8gRTtw2lIKtXzGynRvNqEEb77HD4A+CCCGy2hrZRw4an0AShlq7W9hRGq1shEckzLxQKmr0WQ755UND250d6Z/BLMHB3i+QMK4g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=RUeiY8c0; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="RUeiY8c0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C4CF61F000C4; Sat, 17 Oct 2026 17:32:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1792258350; bh=LEJhjPWulKKxEhdUgm549Eqa825nczXRWKRwDYRBKW8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=RUeiY8c09RErvRFZd16zOwvetR1WxRqm+THrp2NWW1jE8JGHQ+xcPojedhYe4qZRB plYTm7lETjHAAD3FdU7bTzqVsgwnzubUP1k16wVIlNmhwfaMhs+HfseeIR6qgucK2k d2wY39tPrOiu5wZhwootr+JkDPO5Z4keBHHwYY7E= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Perry Yuan , Yifan Zhang , Alex Deucher , Sasha Levin Subject: [PATCH 6.6 0856/1674] drm/amd/pm: Disable MMIO access during SMU Mode 1 reset Date: Sat, 17 Oct 2026 17:52:08 +0200 Message-ID: <20261017160453.094749063@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261017160431.119607952@linuxfoundation.org> References: <20261017160431.119607952@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Perry Yuan [ Upstream commit 0de604d0357d0d22cbf03af1077d174b641707b6 ] During Mode 1 reset, the ASIC undergoes a reset cycle and becomes temporarily inaccessible via PCIe. Any attempt to access MMIO registers during this window (e.g., from interrupt handlers or other driver threads) can result in uncompleted PCIe transactions, leading to NMI panics or system hangs. To prevent this, set the `no_hw_access` flag to true immediately after triggering the reset. This signals other driver components to skip register accesses while the device is offline. A memory barrier `smp_mb()` is added to ensure the flag update is globally visible to all cores before the driver enters the sleep/wait state. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher (cherry picked from commit 7edb503fe4b6d67f47d8bb0dfafb8e699bb0f8a4) Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 427fb7d897a16..ddce6df7eaf53 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4867,6 +4867,9 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev) if (ret) goto mode1_reset_failed; + /* enable mmio access after mode 1 reset completed */ + adev->no_hw_access = false; + amdgpu_device_load_pci_state(adev->pdev); ret = amdgpu_psp_wait_for_bootloader(adev); if (ret) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index fe6c42a736d08..7d9470778a991 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2449,8 +2449,13 @@ static int smu_v13_0_0_mode1_reset(struct smu_context *smu) break; } - if (!ret) + if (!ret) { + /* disable mmio access while doing mode 1 reset*/ + smu->adev->no_hw_access = true; + /* ensure no_hw_access is globally visible before any MMIO */ + smp_mb(); msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); + } return ret; } -- 2.53.0