From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D86E1CCF2C9 for ; Sun, 18 Oct 2026 13:38:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xIR3s-0002Vv-Ae; Sun, 18 Oct 2026 09:36:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xIR3i-0002L6-84 for qemu-devel@nongnu.org; Sun, 18 Oct 2026 09:36:19 -0400 Received: from mail-qv1-xf35.google.com ([2607:f8b0:4864:20::f35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xIR3f-0002Ht-T3 for qemu-devel@nongnu.org; Sun, 18 Oct 2026 09:36:18 -0400 Received: by mail-qv1-xf35.google.com with SMTP id 6a1803df08f44-91b52ba422cso18305126d6.2 for ; Sun, 18 Oct 2026 06:36:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1792330575; x=1792935375; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=WRkaK7EPSULjBJdzew27sq5KHOCEJgvYv+1a4xq91YA=; b=SljF5X9fH3nbwNYXPOoW4XshDiGJ8AiXV4LnT4JyasUWYOCbJ2OnwHLLu5dxmd8a+7 SdqekETopdlOz8Qy7bT3Y4V0llJmUhkBvcUrQg0JpOVDLeYMqPIagbRVnssseoyJVayb OvG+Z1NKTzgtwRetGNYUu3uj7ySvDSY99238yKXBxDeX/YEDzfxitlmvZWpEVUIfo/3P uxojNfXzlQw1vzhp9ss5xdeRwVvPHeNGu/+7gD9V+lxXFQdSFuhWL7/iycQnaHnIXI74 kkN20J5N3yg4WJLClMP278iD839QciVnRf1wBtfnvMSKsRWLLs7se5CjlFseNKYIT9I0 wWlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792330575; x=1792935375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=WRkaK7EPSULjBJdzew27sq5KHOCEJgvYv+1a4xq91YA=; b=YdEvDlM2+Ur5HPfRRsphG/m/fBnNfg29y6wpwsY4GkN5hL7dL7PpZG0p5+zxiNMkXZ W3bnb8vJbbsRuah0LEp1Gj+uH8T4hFH0syn9YkshFdIRmWZid50aRPE39bSwX/aKAeoh ZXEwKIYWh55ni89wrwlXCtcmnoS3PueMwlWwt+cwlG+l6vnrl3MfI/NbSCxMJTTMj+uZ QXlLfMxWoNg0MbuKbH3px7SVUbCxtxY7fVhpEoS0ocSJ37AH1vSqkbS0F5fWHFYoiRvN F8UnEsTGXzfTzOCZ4L8XQEMlM/mGPqVtLzrr4QsmFyTNztTSM+V6bDAuqyS1HKfgGIOP sftQ== X-Gm-Message-State: AFq9FYIHtqCbc9PkYarPDvWqI2r3uD8/2VhCJ8LhiegfcItKHubWNRZL cGv1eulfwMD5oJ9D+EDXO7T+NNlGY5sQXHktJmbcfWJWVO7wECQNS/3YmueEVwIV X-Gm-Gg: AYBFou0hsX5HT1+33QBdbOHZqWDrRPF31v9sStY2pZGvHijOqa8JhwABpXdyhzFbre1 /eHZOuYUoeozmsHrtbyvUkGHFpNz72e9IgyQTlcJUEozlnTT4xHJGkmVo7/0C5ePftR4uZVFkDW wpa424MC3rGTMb2pwEVqvMJUDckgRjkbJzYZsRSP1j17cZbmQ9AJ8W/6Br4cTLXuKhQOGh7kd2O oQ0rKkWz47mKrWnMONpi4qLabeucyLp4PhZdMp0X1DfZV9KNIKyPiudWb3YDV1dCxZAw2TYXYiJ i+roor4mKeHRuB1F3z+xToE45m2Flxr4fWsUGN5Bbvn6YPr8UMYzOI7BOlnsb7J26f37ZL8fOc0 u7ejSboQvqm76wB02xaqUrWqmy9qCNij6fraSmm3ljQqQnk6saEqiQTymx6ZaT4lproh2xqgR3i OyEfDgTTdFvhP9Mg4alYvxmBqPi2OOmbuqDE5iip9BKr0DJLlQG3V3ZNbp6aJ3A+wkqvjNu6dEA PTWqXG1v2F1f8muY2OrRfvu1EOovw7xKdSY4U7CbX33s5e0tgZkPAFRUKWLHKa+tjKYXcE= X-Received: by 2002:a05:620a:44d5:b0:93b:d79f:d941 with SMTP id af79cd13be357-93f29d8c957mr827252785a.54.1792330574732; Sun, 18 Oct 2026 06:36:14 -0700 (PDT) Received: from localhost.localdomain ([2606:6d00:159:2900:ecfc:9d0d:b95b:11bf]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93f2a854bb7sm459056485a.23.2026.10.18.06.36.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 18 Oct 2026 06:36:14 -0700 (PDT) From: Marcelo Manzo To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, philmd@oss.qualcomm.com, Sergey Kambalin , Sergey Kambalin , Marcelo Manzo , Jason Wang Subject: [PATCH v4 09/17] hw/net/bcm2838_genet: add GENET register access macros Date: Sun, 18 Oct 2026 09:35:55 -0400 Message-ID: <20261018133603.64323-10-marcelomanzo@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261018133603.64323-1-marcelomanzo@gmail.com> References: <20261018133603.64323-1-marcelomanzo@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=marcelomanzo@gmail.com; helo=mail-qv1-xf35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Sergey Kambalin Add offsetof()-based byte-offset macros for the register block layouts added in the previous patches (INTRL0/1, UMAC, TDMA/RDMA and their per-ring registers, HFB filters), used by the MMIO read/write dispatch implemented in the following patches. Part of Sergey Kambalin's original Raspberry Pi 4B PCIe/GENET networking series (patchwork series 829638, posted to qemu-devel in 2024, never merged). Carried forward and completed by Marcelo Manzo. Signed-off-by: Sergey Kambalin Signed-off-by: Marcelo Manzo Reviewed-by: Peter Maydell --- include/hw/net/bcm2838_genet.h | 78 ++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/include/hw/net/bcm2838_genet.h b/include/hw/net/bcm2838_genet.h index 2c3c62a9dd..e0add41aab 100644 --- a/include/hw/net/bcm2838_genet.h +++ b/include/hw/net/bcm2838_genet.h @@ -22,9 +22,87 @@ OBJECT_DECLARE_SIMPLE_TYPE(BCM2838GenetState, BCM2838_GENET) #define BCM2838_GENET_DMA_RING_CNT 17 #define BCM2838_GENET_DMA_RING_DEFAULT (BCM2838_GENET_DMA_RING_CNT - 1) +#define BCM2838_GENET_HFB_FILTER_REGS offsetof(BCM2838GenetRegs, hfb) +#define BCM2838_GENET_HFB_FILTER_REG(reg) (BCM2838_GENET_HFB_FILTER_REGS \ + + offsetof(BCM2838GenetRegsHfb, reg)) #define BCM2838_GENET_HFB_FILTER_CNT 48 #define BCM2838_GENET_HFB_FILTER_SIZE 128 +#define BCM2838_GENET_INTRL0_REG(reg) (offsetof(BCM2838GenetRegs, intrl0) \ + + offsetof(BCM2838GenetRegsIntrl0, reg)) +#define BCM2838_GENET_INTRL0_SET BCM2838_GENET_INTRL0_REG(set) +#define BCM2838_GENET_INTRL0_CLEAR BCM2838_GENET_INTRL0_REG(clear) +#define BCM2838_GENET_INTRL0_MASK_SET BCM2838_GENET_INTRL0_REG(mask_set) +#define BCM2838_GENET_INTRL0_MASK_CLEAR BCM2838_GENET_INTRL0_REG(mask_clear) + +#define BCM2838_GENET_INTRL1_REG(reg) (offsetof(BCM2838GenetRegs, intrl1) \ + + offsetof(BCM2838GenetRegsIntrl1, reg)) +#define BCM2838_GENET_INTRL1_SET BCM2838_GENET_INTRL1_REG(set) +#define BCM2838_GENET_INTRL1_CLEAR BCM2838_GENET_INTRL1_REG(clear) +#define BCM2838_GENET_INTRL1_MASK_SET BCM2838_GENET_INTRL1_REG(mask_set) +#define BCM2838_GENET_INTRL1_MASK_CLEAR BCM2838_GENET_INTRL1_REG(mask_clear) + +#define BCM2838_GENET_UMAC_REG(reg) (offsetof(BCM2838GenetRegs, umac) \ + + offsetof(BCM2838GenetRegsUmac, reg)) +#define BCM2838_GENET_UMAC_CMD BCM2838_GENET_UMAC_REG(cmd) +#define BCM2838_GENET_UMAC_MAC0 BCM2838_GENET_UMAC_REG(mac0) +#define BCM2838_GENET_UMAC_MAC1 BCM2838_GENET_UMAC_REG(mac1) +#define BCM2838_GENET_UMAC_MDIO_CMD BCM2838_GENET_UMAC_REG(mdio_cmd) + +#define BCM2838_GENET_TDMA_REGS offsetof(BCM2838GenetRegs, tdma) +#define BCM2838_GENET_TDMA_REG(reg) (BCM2838_GENET_TDMA_REGS \ + + offsetof(BCM2838GenetRegsTdma, reg)) +#define BCM2838_GENET_TDMA_RINGS BCM2838_GENET_TDMA_REG(rings) +#define BCM2838_GENET_TDMA_RING_CFG BCM2838_GENET_TDMA_REG(ring_cfg) +#define BCM2838_GENET_TDMA_CTRL BCM2838_GENET_TDMA_REG(ctrl) +#define BCM2838_GENET_TDMA_STATUS BCM2838_GENET_TDMA_REG(status) + +#define BCM2838_GENET_RDMA_REGS offsetof(BCM2838GenetRegs, rdma) +#define BCM2838_GENET_RDMA_REG(reg) (BCM2838_GENET_RDMA_REGS \ + + offsetof(BCM2838GenetRegsRdma, reg)) +#define BCM2838_GENET_RDMA_RINGS BCM2838_GENET_RDMA_REG(rings) +#define BCM2838_GENET_RDMA_RING_CFG BCM2838_GENET_RDMA_REG(ring_cfg) +#define BCM2838_GENET_RDMA_CTRL BCM2838_GENET_RDMA_REG(ctrl) +#define BCM2838_GENET_RDMA_STATUS BCM2838_GENET_RDMA_REG(status) + +#define BCM2838_GENET_TRING_REG(reg) offsetof(BCM2838GenetTdmaRing, reg) +#define BCM2838_GENET_TRING_WRITE_PTR BCM2838_GENET_TRING_REG(write_ptr) +#define BCM2838_GENET_TRING_WRITE_PTR_HI BCM2838_GENET_TRING_REG(write_ptr_hi) +#define BCM2838_GENET_TRING_PROD_INDEX BCM2838_GENET_TRING_REG(prod_index) +#define BCM2838_GENET_TRING_CONS_INDEX BCM2838_GENET_TRING_REG(cons_index) +#define BCM2838_GENET_TRING_RING_BUF_SIZE BCM2838_GENET_TRING_REG(ring_buf_size) +#define BCM2838_GENET_TRING_RING_START_ADDR BCM2838_GENET_TRING_REG(start_addr) +#define BCM2838_GENET_TRING_RING_START_ADDR_HI BCM2838_GENET_TRING_REG(start_addr_hi) +#define BCM2838_GENET_TRING_RING_END_ADDR BCM2838_GENET_TRING_REG(end_addr) +#define BCM2838_GENET_TRING_RING_END_ADDR_HI BCM2838_GENET_TRING_REG(end_addr_hi) +#define BCM2838_GENET_TRING_RING_MBUF_DONE_TRESH BCM2838_GENET_TRING_REG(mbuf_done_tresh) +#define BCM2838_GENET_TRING_RING_FLOW_PERIOD BCM2838_GENET_TRING_REG(flow_period) +#define BCM2838_GENET_TRING_RING_READ_PTR BCM2838_GENET_TRING_REG(read_ptr) +#define BCM2838_GENET_TRING_RING_READ_PTR_HI BCM2838_GENET_TRING_REG(read_ptr_hi) + +#define BCM2838_GENET_RRING_REG(reg) offsetof(BCM2838GenetRdmaRing, reg) +#define BCM2838_GENET_RRING_WRITE_PTR BCM2838_GENET_RRING_REG(write_ptr) +#define BCM2838_GENET_RRING_WRITE_PTR_HI BCM2838_GENET_RRING_REG(write_ptr_hi) +#define BCM2838_GENET_RRING_PROD_INDEX BCM2838_GENET_RRING_REG(prod_index) +#define BCM2838_GENET_RRING_CONS_INDEX BCM2838_GENET_RRING_REG(cons_index) +#define BCM2838_GENET_RRING_RING_BUF_SIZE BCM2838_GENET_RRING_REG(ring_buf_size) +#define BCM2838_GENET_RRING_RING_START_ADDR BCM2838_GENET_RRING_REG(start_addr) +#define BCM2838_GENET_RRING_RING_START_ADDR_HI BCM2838_GENET_RRING_REG(start_addr_hi) +#define BCM2838_GENET_RRING_RING_END_ADDR BCM2838_GENET_RRING_REG(end_addr) +#define BCM2838_GENET_RRING_RING_END_ADDR_HI BCM2838_GENET_RRING_REG(end_addr_hi) +#define BCM2838_GENET_RRING_RING_MBUF_DONE_TRESH BCM2838_GENET_RRING_REG(mbuf_done_tresh) +#define BCM2838_GENET_RRING_RING_XON_XOFF_TRESH BCM2838_GENET_RRING_REG(xon_xoff_tresh) +#define BCM2838_GENET_RRING_RING_READ_PTR BCM2838_GENET_RRING_REG(read_ptr) +#define BCM2838_GENET_RRING_RING_READ_PTR_HI BCM2838_GENET_RRING_REG(read_ptr_hi) + + +#define BCM2838_GENET_PHY_REG(reg) (offsetof(BCM2838GenetPhyRegs, reg) / 2) +#define BCM2838_GENET_PHY_BMCR BCM2838_GENET_PHY_REG(bmcr) +#define BCM2838_GENET_PHY_AUX_CTL BCM2838_GENET_PHY_REG(aux_ctl) +#define BCM2838_GENET_PHY_SHD BCM2838_GENET_PHY_REG(shd) +#define BCM2838_GENET_EXP_DATA BCM2838_GENET_PHY_REG(exp_data) +#define BCM2838_GENET_EXP_SEL BCM2838_GENET_PHY_REG(exp_ctrl) + #define BCM2838_GENET_PHY_AUX_CTL_MISC 0x7 #define BCM2838_GENET_PHY_AUX_CTL_REGS_SIZE 8 -- 2.55.0