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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1831b37ce3fsm27157689c88.14.2026.10.19.12.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 12:24:42 -0700 (PDT) Date: Mon, 19 Oct 2026 12:24:35 -0700 From: Jonathan Cameron To: Pierre Gondois Cc: linux-kernel@vger.kernel.org, James Morse , Mark Brown , "Rafael J. Wysocki" , Len Brown , Tony Luck , Borislav Petkov , Hanjun Guo , Mauro Carvalho Chehab , Shuai Xue , Maciej Wieczor-Retman , Pawel Chmielewski , Dave Jiang , "Fabio M. De Francesco" , Breno Leitao , Terry Bowman , Dan Williams , Ard Biesheuvel , Morduan Zang , linux-acpi@vger.kernel.org, linux-edac@vger.kernel.org, acpica-devel@lists.linux.dev Subject: Re: [PATCH 5/6] ACPI: APEI: add separate Memory Error Section 2 handlers Message-ID: <20261019122435.000079c0@oss.qualcomm.com> In-Reply-To: <20261019145643.1877246-6-pierre.gondois@arm.com> References: <20261019145643.1877246-1-pierre.gondois@arm.com> <20261019145643.1877246-6-pierre.gondois@arm.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE5MDA3NyBTYWx0ZWRfX2GvmY79l8eeK X65JL/YL/cRG77oLRW9CWwqgkWQTVZXl8rqXjJiLvdTyJ7lwUSsvMe9LmJkjTSAvqstbEhN2MDr pcX9mTiqwg59QYtBjJ/im9rhNa+ODXyHZsp5DyUJSWWqyQzjrSjGGTGJP/Te9eXU2PJ16uVb4Gu srKRaL84vKoNDX66K0v2fSdsPeI2T/o1wgJKhDP6MMn45LGM61gErrwHQ42di1KJ0CJSot6nj7B LLwoQ8k/UHHwoUB8DJYH23bxkQLQhkYarpFrrs+P292joW0eHOuZSHCXLKMpdSPB7C7+OCZ11b/ om0EN0EpN+PAuULgGkH0eW8Kscuh4hhuBki5FEJblSrIb9eHODcU5BDXFwRoYeDGHKhMfVDb2lv GJQ5jV0HQiPaoLVdTQxEbiA/UOmPKao8vheM/5PsUa0jNbh30dKLgCJaPdle8j+WddAv6zfSn4A 0POBbwdzpmcf1Z+q+wg== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE5MDA3NyBTYWx0ZWRfX5XwN1ZpA3lSz jIOtF1oQDkQ4SjiPW7oWd0mX5kN7cT7cTYOIl572ZF0ArMTrMV35klEscjovLXSeO+ChRMVnB0+ XLKEzg9sOdajO7YEpgbk0aiCsMnkiTQ= X-Proofpoint-ORIG-GUID: FIB4ucyPRrBW4yjsTEJ0mf71kfXwjA0L X-Authority-Analysis: v=2.4 cv=Qr/LTlyd c=1 sm=1 tr=0 ts=6ad66e7c cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=7CQSdrXTAAAA:8 a=rtJ9AlOumMsWe6EQo_MA:9 a=CjuIK1q_8ugA:10 a=vr4QvYf-bLy2KjpDp97w:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-GUID: FIB4ucyPRrBW4yjsTEJ0mf71kfXwjA0L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-19_05,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 impostorscore=0 spamscore=0 adultscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610190077 On Mon, 19 Oct 2026 16:56:12 +0200 Pierre Gondois wrote: > Add dedicated GHES and EDAC callbacks for Memory Error Section 2 > records. Use a separate GHES notifier chain so existing consumers > continue to receive legacy memory error sections. > > Signed-off-by: Pierre Gondois A few trivial things inline. Otherwise I'm fine with this though as you noted before the duplicating is a bit annoying. > --- > drivers/acpi/apei/ghes.c | 49 ++++++++++++- > drivers/edac/ghes_edac.c | 150 +++++++++++++++++++++++++++++++++++++++ > include/acpi/ghes.h | 2 + > 3 files changed, 200 insertions(+), 1 deletion(-) > > diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c > index fe10ab0e02f6..c7fb15543b56 100644 > --- a/drivers/acpi/apei/ghes.c > +++ b/drivers/acpi/apei/ghes.c > diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c > index d80c88818691..b18460ba8f40 100644 > --- a/drivers/edac/ghes_edac.c > +++ b/drivers/edac/ghes_edac.c > + > +static int ghes_edac_report_mem_error2(struct notifier_block *nb, > + unsigned long val, void *data) > +{ > + struct cper_sec_mem_err2 *mem_err = data; > + struct edac_raw_error_desc *e; > + struct mem_ctl_info *mci; > + unsigned long sev = val; > + struct ghes_pvt *pvt; > + unsigned long flags; > + char *p; > + > + /* > + * We can do the locking below because GHES defers error processing > + * from NMI to IRQ context. Whenever that changes, we'd at least > + * know. > + */ > + if (WARN_ON_ONCE(in_nmi())) > + return NOTIFY_OK; > + > + spin_lock_irqsave(&ghes_lock, flags); Perhaps use a guard so you can simplify error paths a little. > + > + pvt = ghes_pvt; > + if (!pvt) > + goto unlock; > + > + mci = pvt->mci; > + e = &mci->error_desc; > + > + /* Cleans the error report buffer */ > + memset(e, 0, sizeof(*e)); > + e->error_count = 1; > + e->grain = 1; > + e->msg = pvt->msg; > + e->other_detail = pvt->other_detail; > + e->top_layer = -1; > + e->mid_layer = -1; > + e->low_layer = -1; > + *pvt->other_detail = '\0'; > + *pvt->msg = '\0'; > + > + switch (sev) { > + case GHES_SEV_CORRECTED: > + e->type = HW_EVENT_ERR_CORRECTED; > + break; > + case GHES_SEV_RECOVERABLE: > + e->type = HW_EVENT_ERR_UNCORRECTED; > + break; > + case GHES_SEV_PANIC: > + e->type = HW_EVENT_ERR_FATAL; > + break; > + default: > + case GHES_SEV_NO: > + e->type = HW_EVENT_ERR_INFO; > + } > + Almost everything down to here is not memerr2 specific maybe factor out an initialization helper for the edac structure? > + edac_dbg(1, "error validation_bits: 0x%08llx\n", > + (long long)mem_err->validation_bits); > + > + /* Error type, mapped on e->msg */ > + if (mem_err->validation_bits & CPER_MEM2_VALID_ERROR_TYPE) { > + u8 etype = mem_err->error_type; > + > + p = pvt->msg; > + p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype)); > + } else { > + strscpy(pvt->msg, "unknown error"); > + } > + > + /* Error address */ > + if (mem_err->validation_bits & CPER_MEM2_VALID_PA) { > + e->page_frame_number = PHYS_PFN(mem_err->physical_addr); > + e->offset_in_page = offset_in_page(mem_err->physical_addr); > + } > + > + /* Error grain */ > + if (mem_err->validation_bits & CPER_MEM2_VALID_PA_MASK) > + e->grain = ~mem_err->physical_addr_mask + 1; > + > + /* Memory error location, mapped on e->location */ > + p = e->location; > + p += cper_mem_err2_location(mem_err, p); > + > + if (mem_err->validation_bits & CPER_MEM2_VALID_MODULE_HANDLE) { > + struct dimm_info *dimm = NULL; > + > + p += cper_dimm_err2_location(mem_err, p); > + if (mem_err->mem_dev_handle <= U16_MAX) > + dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle); > + else > + pr_warn(FW_WARN "Memory Error Section 2 module handle 0x%x exceeds SMBIOS range\n", > + mem_err->mem_dev_handle); > + if (dimm) { > + e->top_layer = dimm->idx; > + strscpy(e->label, dimm->label); > + } > + } > + if (p > e->location) > + *(p - 1) = '\0'; > + > + if (!*e->label) > + strscpy(e->label, "unknown memory"); > + > + /* All other fields are mapped on e->other_detail */ > + p = pvt->other_detail; > + p += print_mem_error2_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN); > + if (p > pvt->other_detail) > + *(p - 1) = '\0'; > + > + edac_raw_mc_handle_error(e); > + > +unlock: > + spin_unlock_irqrestore(&ghes_lock, flags); > + > + return NOTIFY_OK; > +}