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836BF1F000C6; Mon, 19 Oct 2026 14:00:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1792418428; bh=CDyUvjRFuY6gb/FANiwi4tYUqLnklY0TRx7rrQv5F9E=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BLidLT4/lGMMuz3I+Yx/yaHIzQjxenx0c4/kA21a9Z7c48Nkv6AeV0jjIcyguY3UD mxUUabP7m1WdQu4n4GsiHY2hAoBfwtID7XB+YwBdWFgpGC0WaqdCUyfCyDQU71kCTk uwV1sJ2ZPGWrtWmplpc5JBpdEvQkywTVbiYoolJJxy6eSJbsPLBmUNL+0TpLMsJdrT d0U/VQ0GecWNIUJECjX1xxjow9XWa3cVsxgVY/hZHS3sXU/RM1fRmz03pDpVC66OOa G4c8OUF8bJ3v31W3oMR9gSlN1t47EVuXi7yqN4NgLiFxdmjYjlzwlRQsoxBI/CnF7O 7MhfkTnCBtyHw== From: Sasha Levin To: patches@lists.linux.dev, stable@vger.kernel.org Cc: Yong-Xuan Wang , Samuel Holland , Paul Walmsley , Sasha Levin , palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH AUTOSEL 6.18] RISC-V: errata: Add SiFive MAL-9092 workaround Date: Mon, 19 Oct 2026 09:48:53 -0400 Message-ID: <20261019135441.1420968-242-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261019135441.1420968-1-sashal@kernel.org> References: <20261019135441.1420968-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.18.57 X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RnJvbTogWW9uZy1YdWFuIFdhbmcgPHlvbmd4dWFuLndhbmdAc2lmaXZlLmNvbT4KClsgVXBzdHJl YW0gY29tbWl0IDE0OGFiODczZDgxOTRjYjQ0ZjI5NDc0ZGEzYjQ0MjhmYTJlMTAwZDEgXQoKU2lG aXZlIGNvcmVzIHdpdGggTUFMLTkwOTIgcmVxdWlyZSBmZW5jZS5ydyBpbnN0cnVjdGlvbnMgYXJv dW5kCkhMVi9ITFZYL0hTViBoeXBlcnZpc29yIGluc3RydWN0aW9ucyB0byBlbnN1cmUgcHJvcGVy IG1lbW9yeSBvcmRlcmluZwp3aGVuIGFjY2Vzc2luZyBndWVzdCBtZW1vcnkuCgpOb3RlIHRoYXQg SFNUQVRVUy5IVSBpcyBjbGVhcmVkIGR1cmluZyBLVk0gaW5pdGlhbGl6YXRpb24sIHJlc3RyaWN0 aW5nCmh5cGVydmlzb3IgaW5zdHJ1Y3Rpb25zIHRvIEhTLW1vZGUgb25seS4gSWYgZnV0dXJlIGNo YW5nZXMgZW5hYmxlCkhTVEFUVVMuSFUgZm9yIFUtbW9kZSBhY2Nlc3MsIGFkZGl0aW9uYWwgZXJy YXRhIGNvbnNpZGVyYXRpb25zIHdpbGwgYmUKbmVlZGVkLgoKU2lnbmVkLW9mZi1ieTogWW9uZy1Y dWFuIFdhbmcgPHlvbmd4dWFuLndhbmdAc2lmaXZlLmNvbT4KUmV2aWV3ZWQtYnk6IFNhbXVlbCBI b2xsYW5kIDxzYW11ZWwuaG9sbGFuZEBzaWZpdmUuY29tPgpMaW5rOiBodHRwczovL3BhdGNoLm1z Z2lkLmxpbmsvMjAyNjA4MTctc2lmaXZlLWVycmF0YS12MS0xLTZhODBmMWEyNzQzZEBzaWZpdmUu Y29tClNpZ25lZC1vZmYtYnk6IFBhdWwgV2FsbXNsZXkgPHBqd0BrZXJuZWwub3JnPgpTaWduZWQt b2ZmLWJ5OiBTYXNoYSBMZXZpbiA8c2FzaGFsQGtlcm5lbC5vcmc+Ci0tLQoKTExNIEdlbmVyYXRl ZCBleHBsYW5hdGlvbnMsIG1heSBiZSBjb21wbGV0ZWx5IGJvZ3VzOgoKVGhlIGxvY2FsIHRyZWUg aXMgKio2LjE4LnkqKiAoYHY2LjE4LjU3YCkuIFRoaXMgU2lGaXZlIE1BTC05MDkyIGNoYW5nZQpp cyBhIGhhcmR3YXJlLWVycmF0YSB3b3JrYXJvdW5kIGZvciBLVk0gZ3Vlc3QtbWVtb3J5IGFjY2Vz c2VzLCBhbmQgdGhlCmNvZGUgaXQgcGF0Y2hlcyBpcyBhbHJlYWR5IGluIHRoaXMgc2VyaWVzLgoK PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09ClBIQVNFIDE6IENPTU1JVCBNRVNTQUdFIEZPUkVOU0lDUwo9PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KCioqU3RlcCAx LjE6IFBBUlNFIFRIRSBTVUJKRUNUIExJTkUqKgoKUmVjb3JkOiBbc3Vic3lzdGVtOiBSSVNDLVYg ZXJyYXRhL1NpRml2ZV0gW2FjdGlvbiB2ZXJiOiBBZGRdIFt3b3JrYXJvdW5kCmZvciBTaUZpdmUg TUFMLTkwOTI6IGBmZW5jZS5yd2AgYXJvdW5kIEhMVi9ITFZYL0hTVl0KCioqU3RlcCAxLjI6IFBB UlNFIEFMTCBDT01NSVQgTUVTU0FHRSBUQUdTKioKClJlY29yZDoKLSBObyBgRml4ZXM6YCB0YWcg KGV4cGVjdGVkIGZvciB0aGlzIHJldmlldyBxdWV1ZSkKLSBObyBgUmVwb3J0ZWQtYnk6YCAvIGBU ZXN0ZWQtYnk6YCAvIGBBY2tlZC1ieTpgCi0gYFJldmlld2VkLWJ5OiBTYW11ZWwgSG9sbGFuZCA8 c2FtdWVsLmhvbGxhbmRAc2lmaXZlLmNvbT5gIChTaUZpdmUsCiAgc2FtZSB2ZW5kb3IpCi0gYExp bms6IGh0dHBzOi8vcGF0Y2gubXNnaWQubGluay8yMDI2MDgxNy1zaWZpdmUtCiAgZXJyYXRhLXYx LTEtNmE4MGYxYTI3NDNkQHNpZml2ZS5jb21gCi0gYFNpZ25lZC1vZmYtYnk6IFlvbmctWHVhbiBX YW5nIDx5b25neHVhbi53YW5nQHNpZml2ZS5jb20+YCAoYXV0aG9yLAogIFNpRml2ZSkKLSBgU2ln bmVkLW9mZi1ieTogUGF1bCBXYWxtc2xleSA8cGp3QGtlcm5lbC5vcmc+YCAoUklTQy1WIGFyY2gK ICBtYWludGFpbmVyKQotIE5vIGBDYzogc3RhYmxlQHZnZXIua2VybmVsLm9yZ2AgKGV4cGVjdGVk OyBub3QgYSBuZWdhdGl2ZSBzaWduYWwpCi0gU2FzaGEgTGV2aW4gU09CIGlnbm9yZWQgcGVyIGlu c3RydWN0aW9ucwoKKipTdGVwIDEuMzogQU5BTFlaRSBUSEUgQ09NTUlUIEJPRFkgVEVYVCoqCgpS ZWNvcmQ6Ci0gW0J1Z10gU2lGaXZlIGNvcmVzIHdpdGggTUFMLTkwOTIgZG8gbm90IHByb3ZpZGUg dGhlIHJlcXVpcmVkIG1lbW9yeQogIG9yZGVyaW5nIGFyb3VuZCBoeXBlcnZpc29yIGxvYWQvc3Rv cmUgKGBITFZgL2BITFZYYC9gSFNWYCkgd2hlbgogIHRvdWNoaW5nIGd1ZXN0IG1lbW9yeS4KLSBb U3ltcHRvbV0gV3Jvbmcvc3RhbGUgZ3Vlc3QgaW5zdHJ1Y3Rpb24gb3IgZGF0YSBvYnNlcnZlZCBi eSB0aGUgaG9zdAogIGh5cGVydmlzb3IgKEtWTSB1bnByaXZpbGVnZWQgZ3Vlc3QtbWVtb3J5IGFj Y2VzcykuIE5vdCBhIGRvY3VtZW50ZWQKICBvb3BzOyBpdCBpcyBhbiBhcmNoaXRlY3R1cmUtbGV2 ZWwgb3JkZXJpbmcgaG9sZS4KLSBbVmVyc2lvbl0gTm9uZSBzdGF0ZWQuIFBhdWwgcXVldWVkIGl0 IGZvciB2Ny4zLXJjLiBBZmZlY3RlZCBgbWltcGlkYAogIHZhbHVlcyBsb29rIGxpa2UgMjAyNS0x MC0zMSwgMjAyNS0xMi0xNywgYW5kIDIwMjYtMDMtMjAgc2lsaWNvbi4KLSBbUm9vdCBjYXVzZV0g TWlzc2luZyBgZmVuY2UucndgIGFyb3VuZCB0aG9zZSBoeXBlcnZpc29yIGluc3RydWN0aW9ucwog IG9uIHNwZWNpZmljIGBtYXJjaGlkYC9gbWltcGlkYCBjb21iaW5hdGlvbnMuIGBIU1RBVFVTLkhV YCBpcyBsZWZ0CiAgY2xlYXIgaW4gS1ZNIHNldHVwLCBzbyB0aGUgd29ya2Fyb3VuZCBpcyBIUy1t b2RlIG9ubHkuCgoqKlN0ZXAgMS40OiBERVRFQ1QgSElEREVOIEJVRyBGSVhFUyoqCgpSZWNvcmQ6 IE5vdCBhIGRpc2d1aXNlZCBjbGVhbnVwLiBJdCBpcyBhbiBleHBsaWNpdCBoYXJkd2FyZS1lcnJh dGEKd29ya2Fyb3VuZCwgd2hpY2ggaXMgYSBzdGFibGUgZXhjZXB0aW9uIGNhdGVnb3J5IChxdWly a3Mvd29ya2Fyb3VuZHMpLgoKPT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09ClBIQVNFIDI6IERJRkYgQU5BTFlTSVMgLSBMSU5FIEJZ IExJTkUKPT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09CgoqKlN0ZXAgMi4xOiBJTlZFTlRPUlkgVEhFIENIQU5HRVMqKgoKUmVjb3Jk OgotIGBhcmNoL3Jpc2N2L0tjb25maWcuZXJyYXRhYDogKzE0IChgQ09ORklHX0VSUkFUQV9TSUZJ VkVfTUFMXzkwOTJgLAogIGBkZXBlbmRzIG9uIEVSUkFUQV9TSUZJVkUgJiYgNjRCSVRgLCBgZGVm YXVsdCB5YCkKLSBgYXJjaC9yaXNjdi9lcnJhdGEvc2lmaXZlL2VycmF0YS5jYDogKzIwIChgZXJy YXRhX21hbF85MDkyX2NoZWNrX2Z1bmNgCiAgKyBsaXN0IGVudHJ5KQotIGBhcmNoL3Jpc2N2L2lu Y2x1ZGUvYXNtL2VycmF0YV9saXN0X3ZlbmRvcnMuaGA6ICsyLy0xCiAgKGBFUlJBVEFfU0lGSVZF X01BTF85MDkyIDJgLCBgRVJSQVRBX1NJRklWRV9OVU1CRVIgM2ApCi0gYGFyY2gvcmlzY3YvaW5j bHVkZS9hc20vaW5zbi1kZWYuaGA6ICsxMy8tMyAoQUxURVJOQVRJVkUgbm9w4oaSYGZlbmNlCiAg cncscndgIGFyb3VuZCBgSExWWF9IVWAvYEhMVl9XYC9gSExWX0RgKQotIFRvdGFsOiAqKjQgZmls ZXMsICs0OS8tNCoqLiBGdW5jdGlvbnM6IGBlcnJhdGFfbWFsXzkwOTJfY2hlY2tfZnVuY2AKICAo bmV3KSwgYGVycmF0YV9saXN0W11gIChleHRlbmRlZCksIEhMViBtYWNyb3MuIFNjb3BlOiBzaW5n bGUtYXJjaAogIHN1cmdpY2FsIGVycmF0YSwgbm90IGEgcmVmYWN0b3IuCgoqKlN0ZXAgMi4yOiBV TkRFUlNUQU5EIFRIRSBDT0RFIEZMT1cgQ0hBTkdFKioKClJlY29yZDoKLSBQcm9iZTogcHJldmlv dXNseSBvbmx5IENJUC00NTMvQ0lQLTEyMDAuIEFmdGVyLAogIGBtYXJjaGlkPT0weDgwMDAwMDAw MDAwMDAxMDlgIGFuZCBgbWltcGlkYCBpbgogIGB7MHgxOTI1MTAzMSwweDE5MjUxMjE3LDB4MTky NjAzMjB9YCBhbHNvIHNldCBiaXQKICBgRVJSQVRBX1NJRklWRV9NQUxfOTA5MmAuCi0gSExWIG1h Y3JvczogcHJldmlvdXNseSBhIHNpbmdsZSBoeXBlcnZpc29yIGxvYWQuIEFmdGVyLCBgbm9wYCAo b3IKICBwYXRjaGVkIGBmZW5jZSBydyxyd2ApIGJvdGggYmVmb3JlIGFuZCBhZnRlciB0aGUgaW5z dHJ1Y3Rpb24gdmlhIHRoZQogIGV4aXN0aW5nIGBBTFRFUk5BVElWRWAgZnJhbWV3b3JrLgotIE5v cm1hbCBLVk0gcGF0aCAoYGt2bV9yaXNjdl92Y3B1X3VucHJpdl9yZWFkYCksIG5vdCBhbiBlcnJv ciBwYXRoLgogIFVuYWZmZWN0ZWQgQ1BVcyBrZWVwIGBub3BgLgoKKipTdGVwIDIuMzogSURFTlRJ RlkgVEhFIEJVRyBNRUNIQU5JU00qKgoKUmVjb3JkOiBbY2F0ZWdvcnk6IGhhcmR3YXJlIHdvcmth cm91bmQgLyBtZW1vcnktb3JkZXJpbmcgZXJyYXRhXQpbbWVjaGFuaXNtOiBTaUZpdmUgTUFMLTkw OTIgb21pdHMgb3JkZXJpbmcgYXJvdW5kIEhTLW1vZGUgZ3Vlc3QtbWVtb3J5Cmh5cGVydmlzb3Ig b3BzOyBhbHRlcm5hdGl2ZXMgcGF0Y2ggaW4gYGZlbmNlLnJ3YCBvbmx5IG9uIG1hdGNoaW5nIENQ VXNdCgpObyBIU1YgbWFjcm9zIGV4aXN0IGluIHRoaXMgdHJlZTsgd3JhcHBpbmcgSExWL0hMVlgg aXMgdGhlIGNvbXBsZXRlIGluLQp0cmVlIGNvdmVyYWdlLgoKKipTdGVwIDIuNDogQVNTRVNTIFRI RSBGSVggUVVBTElUWSoqCgpSZWNvcmQ6IE1hdGNoZXMgQ0lQLTQ1My9DSVAtMTIwMCBzdHlsZS4g Q1BVLUlEIGdhdGVkLCBgZGVmYXVsdCB5YCwKcmV2aWV3ZWQgYnkgU2lGaXZlIGFuZCBxdWV1ZWQg YnkgdGhlIGFyY2ggbWFpbnRhaW5lci4gUmVncmVzc2lvbiByaXNrIGlzCmxvdzogZXh0cmEgbm9w cyBvbiBvdGhlciBDUFVzOyBmZW5jZXMgb25seSBvbiBsaXN0ZWQgSURzLiBSZXNpZHVhbApyaXNr czogYGluc24tZGVmLmhgIHJlbGllcyBvbiBpbmNsdWRlIG9yZGVyIGZvcgpgQUxURVJOQVRJVkVg L2BTSUZJVkVfVkVORE9SX0lEYC9gRVJSQVRBX1NJRklWRV9NQUxfOTA5MmA7CmB3YXJuX21pc3Nf ZXJyYXRhKClgIGNhbiB3YXJuIGF0IGJvb3QgaWYgS1ZNIGlzIG5vdCBidWlsdC1pbiBiZWNhdXNl IHRoZQpvbmx5IGFsdGVybmF0aXZlIHNpdGVzIGFyZSBpbiBLVk0uCgo9PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KUEhBU0UgMzog R0lUIEhJU1RPUlkgSU5WRVNUSUdBVElPTgo9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KCioqU3RlcCAzLjE6IEJMQU1FIFRIRSBD SEFOR0VEIExJTkVTKioKClJlY29yZDogSExWIG1hY3JvcyBjb21lIGZyb20gYDI2YjczZjE0OTMz ZTljYCAoMjAyMi0xMC0wMiwg4oCccmlzY3Y6IEtWTToKQXBwbHkgaW5zbi1kZWYgdG8gaGx2IGVu Y29kaW5nc+KAnSkuIFNpRml2ZSBlcnJhdGEgcHJvYmUvbGlzdCBmcm9tCmA4MDAxNDlhNzdjMmNi OGAgLyBgYmZmM2ZmNTI1NDYwYjRgICgyMDIxLCBDSVAtNDUzL0NJUC0xMjAwKS4gVGhlCmh5cGVy dmlzb3IgYWNjZXNzb3JzIGhhdmUgYmVlbiBpbiB0cmVlIGZvciB5ZWFyczsgdGhlIGVycmF0YSBp cyBuZXcKc2lsaWNvbiwgbm90IG5ldyBrZXJuZWwgY29kZS4KCioqU3RlcCAzLjI6IEZPTExPVyBU SEUgRklYRVM6IFRBRyoqCgpSZWNvcmQ6IE5vIGBGaXhlczpgIHRhZy4gVGhlIGRlZmVjdCBpcyBp biB0aGUgQ1BVLCBub3QgaW4gYSBwcmlvciBrZXJuZWwKY29tbWl0LiBOb3QgYXBwbGljYWJsZS4K CioqU3RlcCAzLjM6IENIRUNLIEZJTEUgSElTVE9SWSBGT1IgUkVMQVRFRCBDSEFOR0VTKioKClJl Y29yZDogUmVjZW50IGBhcmNoL3Jpc2N2YCBlcnJhdGEgd29yayBpcyBNSVBTIFA4NzAwLCBULUhl YWQKR0hPU1RXUklURSwgdmVuZG9yLWhlYWRlciBzcGxpdCAoYDE2ZDE4ZTNlYWYyOWJgKS4gTm9u ZSBvZiB0aG9zZSBpcyBhCnByZXJlcXVpc2l0ZSBmb3IgdGhpcyBwYXRjaC4gU3RhbmRhbG9uZSB2 MSwgbm90IHBhdGNoIFgvWS4KCioqU3RlcCAzLjQ6IENIRUNLIFRIRSBBVVRIT1InUyBPVEhFUiBD T01NSVRTKioKClJlY29yZDogWW9uZy1YdWFuIFdhbmcgaXMgYSBTaUZpdmUgY29udHJpYnV0b3Ig d2l0aCBSSVNDLVYgS1ZNIHdvcmsgaW4KdGhpcyBoaXN0b3J5IChBUExJQywgU3ZhZGUvU3ZhZHUp LiBTYW11ZWwgSG9sbGFuZCAoU2lGaXZlKSByZXZpZXdlZC4gTm90CnRoZSBhcmNoIG1haW50YWlu ZXI7IFBhdWwgV2FsbXNsZXkgcXVldWVkIGl0LgoKKipTdGVwIDMuNTogQ0hFQ0sgRk9SIERFUEVO REVOVC9QUkVSRVFVSVNJVEUgQ09NTUlUUyoqCgpSZWNvcmQ6IE5lZWRzIFJJU0MtViBhbHRlcm5h dGl2ZXMsIGBFUlJBVEFfU0lGSVZFYCwKYGVycmF0YV9saXN0X3ZlbmRvcnMuaGAsIGFuZCB0aGUg SExWIG1hY3Jvcy4gQWxsIGFyZSBhbmNlc3RvcnMgb2YKYHY2LjE4LjU3YCAoYGdpdCBtZXJnZS1i YXNlIC0taXMtYW5jZXN0b3JgIHN1Y2NlZWRlZCBmb3IgYDE2ZDE4ZTNlYWYyOWJgCmFuZCBgMjZi NzNmMTQ5MzNlOWNgKS4gQXBwbGllcyBzdGFuZGFsb25lLgoKPT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09ClBIQVNFIDQ6IE1BSUxJ TkcgTElTVCBBTkQgRVhURVJOQUwgUkVTRUFSQ0gKPT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09CgoqKlN0ZXAgNC4xOiBGSU5EIFRI RSBPUklHSU5BTCBQQVRDSCBESVNDVVNTSU9OKioKClJlY29yZDoKLSBgYjQgZGlnIC1jIGYzNmVl YWFhZWNjMmNgIOKGkiBodHRwczovL3BhdGNoLm1zZ2lkLmxpbmsvMjAyNjA4MTctc2lmaXZlLQog IGVycmF0YS12MS0xLTZhODBmMWEyNzQzZEBzaWZpdmUuY29tCi0gYGI0IGRpZyAtYWA6ICoqdjEg b25seSoqICgyMDI2LTA4LTE3KS4gTm8gdjIvdjMuCi0gVGhyZWFkOiBwYXRjaCArIFBhdWwgV2Fs bXNsZXkg4oCcVGhhbmtzLCBxdWV1ZWQgZm9yIHY3LjMtcmMu4oCdIE5vIE5BS3MsCiAgbm8gc3Rh YmxlIG5vbWluYXRpb24sIG5vIHJldmlld2VyIHJpc2sgZmxhZ3MuCi0gbG9yZS5rZXJuZWwub3Jn IFdlYkZldGNoIHJldHVybmVkIDQwMzsgdGhyZWFkIHJlY292ZXJlZCB2aWEgYGI0IGRpZwogIC1t YCBtYm94LgoKKipTdGVwIDQuMjogQ0hFQ0sgV0hPIFJFVklFV0VEIFRIRSBQQVRDSCoqCgpSZWNv cmQ6IGBiNCBkaWcgLXdgIFRvL0NjOiBQYXVsIFdhbG1zbGV5LCBQYWxtZXIgRGFiYmVsdCwgQWxi ZXJ0IE91LApBbGV4YW5kcmUgR2hpdGksIFNhbXVlbCBIb2xsYW5kLCBvdGhlciBTaUZpdmUgZW5n aW5lZXJzLCBsaW51eC1yaXNjdiwKbGludXgta2VybmVsLiBBcHByb3ByaWF0ZSBSSVNDLVYgbWFp bnRhaW5lcnMgd2VyZSBvbiB0aGUgcGF0Y2guCgoqKlN0ZXAgNC4zOiBTRUFSQ0ggRk9SIFRIRSBC VUcgUkVQT1JUKioKClJlY29yZDogTm8gc3l6Ym90L2J1Z3ppbGxhL3VzZXIgY3Jhc2ggdGhyZWFk LiBUaGlzIGlzIGEgdmVuZG9yIGVycmF0YQpmcm9tIFNpRml2ZSwgbm90IGEgZnV6emVyIHJlcG9y dC4gUHVibGljIE1BTC05MDkyIGRvY3VtZW50YXRpb24gYmV5b25kCnRoZSBwYXRjaCB3YXMgbm90 IGZvdW5kLgoKKipTdGVwIDQuNDogQ0hFQ0sgRk9SIFJFTEFURUQgUEFUQ0hFUyBBTkQgU0VSSUVT KioKClJlY29yZDogU2luZ2xlIHN0YW5kYWxvbmUgcGF0Y2ggKGBbUEFUQ0hdYCwgbm90IGBbUEFU Q0ggMS9OXWApLiBObwpmb2xsb3ctdXBzIG9uIHRoZXNlIGZpbGVzIGFmdGVyIHRoaXMgY29tbWl0 IG9uIEhFQUQuCgoqKlN0ZXAgNC41OiBDSEVDSyBTVEFCTEUgTUFJTElORyBMSVNUIEhJU1RPUlkq KgoKUmVjb3JkOiBXZWIgc2VhcmNoIG9mIHN0YWJsZS9NQUwtOTA5MiBmb3VuZCBubyBzdGFibGUt bGlzdCBkaXNjdXNzaW9uCmFuZCBubyBzdGF0ZWQgcmVhc29uIHRvIGtlZXAgaXQgb3V0IG9mIHN0 YWJsZS4KCj09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PQpQSEFTRSA1OiBDT0RFIFNFTUFOVElDIEFOQUxZU0lTCj09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PQoKKipT dGVwIDUuMTogSURFTlRJRlkgS0VZIEZVTkNUSU9OUyBJTiBUSEUgRElGRioqCgpSZWNvcmQ6IGBl cnJhdGFfbWFsXzkwOTJfY2hlY2tfZnVuY2AgKG5ldyk7IGBlcnJhdGFfbGlzdFtdYDsgbWFjcm9z CmBBTFRfU0lGSVZFX01BTF85MDkyX0ZFTkNFYCwgYEhMVlhfSFVgLCBgSExWX1dgLCBgSExWX0Rg LiBFeGlzdGluZwpgc2lmaXZlX2VycmF0YV9wcm9iZWAgLyBgc2lmaXZlX2VycmF0YV9wYXRjaF9m dW5jYCBwaWNrIGl0IHVwIHZpYQpgRVJSQVRBX1NJRklWRV9OVU1CRVJgLgoKKipTdGVwIDUuMjog VFJBQ0UgQ0FMTEVSUyoqCgpSZWNvcmQ6Ci0gYEhMVipgIHVzZWQgb25seSBpbiBgYXJjaC9yaXNj di9rdm0vdmNwdV9leGl0LmNgIOKGkgogIGBrdm1fcmlzY3ZfdmNwdV91bnByaXZfcmVhZCgpYAot IENhbGxlcnMgb2YgdGhhdDogYGt2bV9yaXNjdl92Y3B1X3ZpcnR1YWxfaW5zbigpYCBpbiBgdmNw dV9pbnNuLmNgCiAgKGd1ZXN0IGluc24gZmV0Y2ggd2hlbiBgc3R2YWxgIGlzIDAgLyAxNi1iaXQp OyBgdmNwdV9zYmlfdjAxLmNgIChTQkkKICAwLjEgU0VORF9JUEkgLyByZW1vdGUgZmVuY2UgaGFy dC1tYXNrIHJlYWRzKQotIENvbnRleHQ6IEtWTSBWTS1leGl0IGhhbmRsaW5nLCBub3QgSVJRLWVu dHJ5IGNvcmUuIFJlYWNoYWJsZSB3aGVuZXZlcgogIGEgZ3Vlc3QgdHJhcHMuCgoqKlN0ZXAgNS4z OiBUUkFDRSBDQUxMRUVTKioKClJlY29yZDogUHJvYmUgb25seSBjb21wYXJlcyBgYXJjaGlkYC9g aW1waWRgLiBQYXRjaGluZyB1c2VzCmBwYXRjaF90ZXh0X25vc3luY2AgdW5kZXIgYHRleHRfbXV0 ZXhgLCBzYW1lIGFzIENJUCBlcnJhdGEuIE1hY3JvcwpleHBhbmQgdG8gYEFMVEVSTkFUSVZFKCJu b3AiLCAiZmVuY2UgcncsIHJ3IiwgLi4uKWAuCgoqKlN0ZXAgNS40OiBGT0xMT1cgVEhFIENBTEwg Q0hBSU4qKgoKUmVjb3JkOiBVc2Vyc3BhY2UgUUVNVS9LVk0gb24gUklTQy1WIOKGkiBndWVzdCB0 cmFwIOKGkgpga3ZtX3Jpc2N2X3ZjcHVfdW5wcml2X3JlYWRgIOKGkiBITFYvSExWWC4gVW5wcml2 aWxlZ2VkIGd1ZXN0IGNvZGUgY2FuCmluZHVjZSB0aG9zZSBleGl0cy4gT25seSByZWxldmFudCB3 aXRoIGBDT05GSUdfS1ZNYCBvbiBtYXRjaGluZyBTaUZpdmUKY29yZXMuCgoqKlN0ZXAgNS41OiBT RUFSQ0ggRk9SIFNJTUlMQVIgUEFUVEVSTlMqKgoKUmVjb3JkOiBTYW1lIHBhdHRlcm4gYXMgQ0lQ LTQ1MyBhbmQgQ0lQLTEyMDAgaW4gdGhpcyB0cmVlLiBObyBIU1YgbWFjcm9zCmluIGBhcmNoL3Jp c2N2YCBhdCBgdjYuMTguNTdgIG9yIEhFQUQsIHNvIG5vdGhpbmcgZWxzZSB0byB3cmFwIGhlcmUu Cgo9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT0KUEhBU0UgNjogQ1JPU1MtUkVGRVJFTkNJTkcgQUdBSU5TVCBUSEUgTE9DQUwgVFJF RQo9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT0KCioqU3RlcCA2LjE6IERPRVMgVEhFIEJVR0dZIENPREUgRVhJU1QgSU4gVEhJUyBU UkVFPyoqCgpSZWNvcmQ6IFllcy4gTG9jYWwgdHJlZTogYGdpdCBkZXNjcmliZSBIRUFEYCA9CmB2 Ni4xOC41Ny0xNTUtZ2NkZjIzOWNhODg1YjJgLCBgbWFrZSBrZXJuZWx2ZXJzaW9uYCA9ICoqNi4x OC41NyoqLiBgZ2l0Cm1lcmdlLWJhc2UgLS1pcy1hbmNlc3RvciBmMzZlZWFhYWVjYzJjIHY2LjE4 LjU3YCBmYWlsZWQgKHdvcmthcm91bmQgbm90CmluIDYuMTguNTcpLiBgdjYuMTguNTdgIGFscmVh ZHkgaGFzIEhMViBtYWNyb3MgaW4gYGluc24tZGVmLmhgLCBLVk0KYHZjcHVfZXhpdC5jYCwgYW5k IFNpRml2ZSBlcnJhdGEgd2l0aCBgRVJSQVRBX1NJRklWRV9OVU1CRVIgMmAuIFRoZQpoYXJkd2Fy ZSBidWcgaXMgdGhlcmVmb3JlIGxpdmUgZm9yIG1hdGNoaW5nIENQVXMgcnVubmluZyB0aGlzIHNl cmllcy4KCioqU3RlcCA2LjI6IENIRUNLIEZPUiBCQUNLUE9SVCBDT01QTElDQVRJT05TKioKClJl Y29yZDogYGdpdCBkaWZmIC0tc3RhdCB2Ni4xOC41NyBmMzZlZWFhYWVjYzJjIC0tIDx0aGUgZm91 ciBmaWxlcz5gIGlzCmV4YWN0bHkgKzQ5Ly00LiBDbGVhbiBhcHBseS4gTm8gY29uZmxpY3Rpbmcg cmVmYWN0b3IgaW4gNi4xOC41NyB2cyB0aGlzCnBhdGNoLgoKKipTdGVwIDYuMzogQ0hFQ0sgSUYg UkVMQVRFRCBGSVhFUyBBUkUgQUxSRUFEWSBIRVJFKioKClJlY29yZDogYGdpdCBsb2cgLS1ncmVw PU1BTC05MDkyYCBvbmx5IGZpbmRzIHRoaXMgY2FuZGlkYXRlLiBObyBlYXJsaWVyCmVxdWl2YWxl bnQgd29ya2Fyb3VuZC4KCj09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PQpQSEFTRSA3OiBTVUJTWVNURU0gQU5EIE1BSU5UQUlORVIg Q09OVEVYVAo9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT0KCioqU3RlcCA3LjE6IElERU5USUZZIFRIRSBTVUJTWVNURU0gQU5EIElU UyBDUklUSUNBTElUWSoqCgpSZWNvcmQ6IFthcmNoL3Jpc2N2IGVycmF0YSArIEtWTSBndWVzdC1t ZW1vcnkgYWNjZXNzXSBbSU1QT1JUQU5ULCBub3QKQ09SRTogUklTQy1WLXNwZWNpZmljLCBhbmQg b25seSBsaXN0ZWQgU2lGaXZlIGNvcmVzIHdpdGggS1ZNXS4gV3JvbmcKZ3Vlc3QtbWVtb3J5IG9y ZGVyaW5nIGlzIHN0aWxsIGEgcmVhbCB2aXJ0IGNvcnJlY3RuZXNzIGlzc3VlIGZvciB0aG9zZQpz eXN0ZW1zLgoKKipTdGVwIDcuMjogQVNTRVNTIFNVQlNZU1RFTSBBQ1RJVklUWSoqCgpSZWNvcmQ6 IFJJU0MtViBlcnJhdGEgYW5kIEtWTSBhcmUgYWN0aXZlbHkgbWFpbnRhaW5lZC4gVGhpcyBpcyBu ZXctCnNpbGljb24gZXJyYXRhIG9uIGEgbWF0dXJlIEhMVi9LVk0gcGF0aCwgbm90IGEgcmV3cml0 ZSBvZiBhIGJyYW5kLW5ldwpzdWJzeXN0ZW0uCgo9PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KUEhBU0UgODogSU1QQUNUIEFORCBS SVNLIEFTU0VTU01FTlQKPT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09CgoqKlN0ZXAgOC4xOiBERVRFUk1JTkUgV0hPIElTIEFGRkVD VEVEKioKClJlY29yZDogUklTQy1WICsgYENPTkZJR19FUlJBVEFfU0lGSVZFYCAoc2VsZWN0ZWQg YnkgYEFSQ0hfU0lGSVZFYCkgKwpgQ09ORklHXzY0QklUYCArIEtWTSArIGBtYXJjaGlkIDB4ODAw MDAwMDAwMDAwMDEwOWAgd2l0aCBvbmUgb2YgdGhyZWUKYG1pbXBpZGBzLiBEcml2ZXIvcGxhdGZv cm0tc3BlY2lmaWMsIG5vdCB1bml2ZXJzYWwuCgoqKlN0ZXAgOC4yOiBERVRFUk1JTkUgVEhFIFRS SUdHRVIgQ09ORElUSU9OUyoqCgpSZWNvcmQ6IFRyaWdnZXIgaXMgS1ZNIHVzaW5nIEhMVi9ITFZY IHRvIHJlYWQgZ3Vlc3QgbWVtb3J5IChpbnN0cnVjdGlvbgplbXVsYXRlLCBTQkkgMC4xIGhhcnQg bWFza3MpLiBDb21tb24gZm9yIGFueSBWTSBvbiB0aG9zZSBjb3Jlcy4gR3Vlc3QKKHR5cGljYWxs eSB1bnByaXZpbGVnZWQpIGNhbiBjYXVzZSB0aGUgVk0tZXhpdC4gTm90IGEgcmFyZSBlcnJvci1w YXRoLQpvbmx5IGJ1Zy4KCioqU3RlcCA4LjM6IERFVEVSTUlORSBUSEUgRkFJTFVSRSBNT0RFIFNF VkVSSVRZKioKClJlY29yZDogW0ZhaWx1cmUgbW9kZTogbWlzc2luZyBtZW1vcnkgZmVuY2Ug4oaS IHN0YWxlL3dyb25nIGd1ZXN0IGluc24gb3IKZGF0YSBpbiB0aGUgaHlwZXJ2aXNvcl0gW1NldmVy aXR5OiBISUdIIOKAlCBndWVzdCBjb3JydXB0aW9uIG9yIGluY29ycmVjdAplbXVsYXRpb247IG5v dCBhIGRvY3VtZW50ZWQgaG9zdCBwYW5pY10uIFNpbGVudCB3cm9uZ25lc3MgaXMgd29yc2UgdGhh bgphIFdBUk4uCgoqKlN0ZXAgOC40OiBDQUxDVUxBVEUgUklTSy1CRU5FRklUIFJBVElPKioKClJl Y29yZDoKLSBCZW5lZml0OiBISUdIIGZvciBLVk0gb24gdGhlIGxpc3RlZCBTaUZpdmUgY29yZXMg KGNvcnJlY3QgZ3Vlc3QtbWVtb3J5CiAgYWNjZXNzKS4KLSBSaXNrOiBMT1cg4oCUIH41MCBsaW5l cywgSUQtZ2F0ZWQgYWx0ZXJuYXRpdmVzLCBzYW1lIG1lY2hhbmlzbSBhcwogIENJUC0xMjAwIGFs cmVhZHkgaW4gNi4xOC41Ny4gVW5hZmZlY3RlZCBDUFVzIG9ubHkgZ2FpbiBub3BzLgotIFJhdGlv OiBiZW5lZml0IG91dHdlaWdocyByaXNrIGZvciB0aGlzIDYuMTgueSB0cmVlLgoKPT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09ClBI QVNFIDk6IEZJTkFMIFNZTlRIRVNJUwo9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KCioqU3RlcCA5LjE6IENPTVBJTEUgVEhFIEVW SURFTkNFKioKCkZPUjoKLSBIYXJkd2FyZSBlcnJhdGEvcXVpcmssIHdoaWNoIHN0YWJsZSBleHBs aWNpdGx5IGFjY2VwdHMKLSBSZWFsIEtWTSBndWVzdC1tZW1vcnkgb3JkZXJpbmcgYnVnIG9uIHNo aXBwaW5nL3Nvb24tc2hpcHBpbmcgU2lGaXZlCiAgY29yZXMKLSBTbWFsbCAoKzQ5Ly00KSwgdXNl cyBleGlzdGluZyBhbHRlcm5hdGl2ZXMvZXJyYXRhIG1hY2hpbmVyeQotIEhMVi9LVk0vU2lGaXZl IGVycmF0YSBhbGwgcHJlc2VudCBpbiA2LjE4LjU3OyBhcHBsaWVzIGNsZWFubHkKLSBSZXZpZXdl ZCBieSBTaUZpdmUsIHF1ZXVlZCBieSBSSVNDLVYgYXJjaCBtYWludGFpbmVyLCBubyBOQUtzCi0g Q1BVLUlEIG1hdGNoIHNvIG90aGVyIFJJU0MtViBzeXN0ZW1zIGFyZSBub3QgZnVuY3Rpb25hbGx5 IGNoYW5nZWQKCkFHQUlOU1Q6Ci0gTmV3IEtjb25maWcgc3ltYm9sIChzdGFuZGFyZCBmb3IgUklT Qy1WIGVycmF0YSwgYGRlZmF1bHQgeWApCi0gTm8gZmllbGQgY3Jhc2gvc3l6Ym90IHJlcG9ydCAo dmVuZG9yIGVycmF0YSwgdHlwaWNhbCkKLSBQb3NzaWJsZSBgd2Fybl9taXNzX2VycmF0YWAgbm9p c2UgaWYgS1ZNIGlzIGRpc2FibGVkIG9uIGFuIGFmZmVjdGVkCiAgQ1BVCi0gSFNWIG1lbnRpb25l ZCBpbiB0ZXh0IGJ1dCBubyBIU1YgbWFjcm9zIGhlcmUgKG5vdCBhIGZ1bmN0aW9uYWwgZ2FwIGlu CiAgNi4xOC55KQoKVU5SRVNPTFZFRDoKLSBQdWJsaWMgTUFMLTkwOTIgZGF0YXNoZWV0IHRleHQg d2FzIG5vdCBmb3VuZCAob25seSB0aGUga2VybmVsIHBhdGNoKQotIGxvcmUua2VybmVsLm9yZyBI VFRQIDQwMzsgZGlzY3Vzc2lvbiByZWNvdmVyZWQgZnJvbSBiNCBtYm94IGluc3RlYWQKCioqU3Rl cCA5LjI6IEFQUExZIFRIRSBTVEFCTEUgUlVMRVMgQ0hFQ0tMSVNUKioKCjEuIE9idmlvdXNseSBj b3JyZWN0IGFuZCB0ZXN0ZWQ/ICoqUEFTUyoqIOKAlCBJRC1nYXRlZCBhbHRlcm5hdGl2ZSBmZW5j ZXM7CiAgIFNpRml2ZSByZXZpZXc7IG1haW50YWluZXIgcXVldWVkIGZvciA3LjMtcmMKMi4gRml4 ZXMgYSByZWFsIGJ1ZyB0aGF0IGFmZmVjdHMgdXNlcnM/ICoqUEFTUyoqIOKAlCBLVk0gZ3Vlc3Qt bWVtb3J5CiAgIG9yZGVyaW5nIG9uIGxpc3RlZCBjb3JlcwozLiBJbXBvcnRhbnQgaXNzdWU/ICoq UEFTUyoqIOKAlCBISUdIOiBpbmNvcnJlY3QgaHlwZXJ2aXNvciBndWVzdAogICBpbnN0cnVjdGlv bi9kYXRhIHJlYWRzIChjb3JydXB0aW9uIC8gYmFkIGVtdWxhdGlvbikKNC4gU21hbGwgYW5kIGNv bnRhaW5lZD8gKipQQVNTKiog4oCUIDQgZmlsZXMsICs0OS8tNAo1LiBObyBuZXcgZmVhdHVyZXMg b3IgQVBJcz8gKipQQVNTKiog4oCUIG5vIHVzZXJzcGFjZSBBQkk7IEtjb25maWcgaXMgdGhlCiAg IHVzdWFsIGVycmF0YSB0b2dnbGUKNi4gQ2FuIGFwcGx5IHRvIHRoZSBsb2NhbCB0cmVlPyAqKlBB U1MqKiDigJQgY2xlYW4gdnMgYHY2LjE4LjU3YAoKKipTdGVwIDkuMzogQ0hFQ0sgRk9SIEVYQ0VQ VElPTiBDQVRFR09SSUVTKioKClJlY29yZDogSGFyZHdhcmUgcXVpcmsvd29ya2Fyb3VuZCAoU2lG aXZlIENQVSBlcnJhdGEpLCBzYW1lIGNsYXNzIGFzClVTQi9QQ0kgcXVpcmtzIGFuZCBleGlzdGlu ZyBDSVAtNDUzL0NJUC0xMjAwLgoKKipTdGVwIDkuNDogREVDSVNJT04qKgoKVGhpcyBiZWxvbmdz IG9uICoqdGhpcyoqIDYuMTgueSB0cmVlLiBUaGUgSExWIHBhdGggaGFzIGJlZW4gaGVyZSBzaW5j ZQoyMDIyOyA2LjE4LjU3IGp1c3QgbGFja3MgdGhlIGZlbmNlIHdvcmthcm91bmQuIExUUyB1c2Vy cyB3aG8gcnVuIEtWTSBvbgp0aGVzZSBTaUZpdmUgY29yZXMgZ2V0IGEgY29udGFpbmVkLCBJRC1n YXRlZCBmaXggd2l0aCB0aGUgc2FtZSBzaGFwZSBhcwplcnJhdGEgYWxyZWFkeSBpbiB0aGUgc2Vy aWVzLgoKVmVyaWZpY2F0aW9uOgotIFtQaGFzZSAxXSBQYXJzZWQgdGFnczogUmV2aWV3ZWQtYnkg U2FtdWVsIEhvbGxhbmQ7IExpbmsgdG8gbXNnaWQKICAyMDI2MDgxNy1zaWZpdmUtZXJyYXRhLXYx LTE7IFNPQiBZb25nLVh1YW4gV2FuZyBhbmQgUGF1bCBXYWxtc2xleTsgbm8KICBGaXhlcy9SZXBv cnRlZC1ieS9DYzpzdGFibGUKLSBbUGhhc2UgMl0gRGlmZjogKzQ5Ly00IGFjcm9zcyBLY29uZmln LmVycmF0YSwgZXJyYXRhLmMsCiAgZXJyYXRhX2xpc3RfdmVuZG9ycy5oLCBpbnNuLWRlZi5oOyBB TFRFUk5BVElWRSBub3DihpJmZW5jZSBhcm91bmQKICBITFZYX0hVL0hMVl9XL0hMVl9ECi0gW1Bo YXNlIDNdIGdpdCBibGFtZSB2Ni4xOC41NyBpbnNuLWRlZi5oOiBITFYgbWFjcm9zIGZyb20KICAy NmI3M2YxNDkzM2U5YyAoMjAyMik7IGVycmF0YSBmcmFtZXdvcmsgZnJvbSAyMDIxIENJUCBjb21t aXRzCi0gW1BoYXNlIDNdIE5vIEZpeGVzOiB0YWc7IHN0YW5kYWxvbmUsIG5vdCBhIHNlcmllcwot IFtQaGFzZSAzXSBnaXQgbWVyZ2UtYmFzZSAtLWlzLWFuY2VzdG9yIDI2YjczZjE0OTMzZTljIHY2 LjE4LjU3IOKGkiB5ZXM7CiAgMTZkMThlM2VhZjI5YiB2Ni4xOC41NyDihpIgeWVzCi0gW1BoYXNl IDRdIGI0IGRpZyAtYyBmMzZlZWFhYWVjYzJjOiBsb3JlIFVSTCBmb3VuZDsgLWE6IHYxIG9ubHk7 IC13OgogIFJJU0MtViBtYWludGFpbmVycyBvbiBUby9DYzsgbWJveDogUGF1bCDigJxxdWV1ZWQg Zm9yIHY3LjMtcmPigJ07IG5vIE5BSwotIFtQaGFzZSA0XSBsb3JlIFdlYkZldGNoIDQwMzsgbWJv eCB1c2VkIGluc3RlYWQKLSBbUGhhc2UgNV0gSExWKiBvbmx5IHVzZWQgaW4ga3ZtL3ZjcHVfZXhp dC5jOyBjYWxsZXJzIHZjcHVfaW5zbi5jIGFuZAogIHZjcHVfc2JpX3YwMS5jOyBnaXQgZ3JlcCBI U1ZfIGluIGFyY2gvcmlzY3Y6IG5vbmUKLSBbUGhhc2UgNl0gZ2l0IGRlc2NyaWJlIEhFQUQ6IHY2 LjE4LjU3LTE1NS1nY2RmMjM5Y2E4ODViMjsKICBrZXJuZWx2ZXJzaW9uIDYuMTguNTcKLSBbUGhh c2UgNl0gZ2l0IG1lcmdlLWJhc2UgLS1pcy1hbmNlc3RvciBmMzZlZWFhYWVjYzJjIHY2LjE4LjU3 IOKGkiBub3QgaW4KICA2LjE4LjU3OyBnaXQgZ3JlcCBNQUwtOTA5MiB2Ni4xOC41NyDihpIgbm9u ZQotIFtQaGFzZSA2XSBnaXQgZGlmZiAtLXN0YXQgdjYuMTguNTcgZjM2ZWVhYWFlY2MyYyAtLSB0 aGUgZm91ciBmaWxlcyDihpIKICBleGFjdCBwYXRjaCwgY2xlYW4gYXBwbHkKLSBbUGhhc2UgN10g QVJDSF9TSUZJVkUgc2VsZWN0cyBFUlJBVEFfU0lGSVZFOyBLVk0gaXMKICBhcmNoL3Jpc2N2L2t2 bS9LY29uZmlnCi0gW1BoYXNlIDhdIEZhaWx1cmUgbW9kZTogbWlzc2luZyBmZW5jZSDihpIgd3Jv bmcgZ3Vlc3QgbWVtb3J5IGluIEtWTSwKICBzZXZlcml0eSBISUdICi0gVU5WRVJJRklFRDogZnVs bCBwdWJsaWMgTUFMLTkwOTIgc2lsaWNvbiBtYW51YWw7IGNvbXBpbGUgb2YKICB2Y3B1X2V4aXQu YyB3YXMgaW5mZXJyZWQgZnJvbSBpbmNsdWRlIG9yZGVyLCBub3QgYnkgYnVpbGRpbmcKClRoZSB3 b3JrYXJvdW5kIGlzIHNtYWxsLCBJRC1nYXRlZCwgYW5kIGZpeGVzIGEgcmVhbCBLVk0gbWVtb3J5 LW9yZGVyaW5nCmVycmF0dW0gb24gaGFyZHdhcmUgdGhhdCA2LjE4LnkgY2FuIGJvb3QuIEl0IG1l ZXRzIHRoZSBzdGFibGUgcnVsZXMgYW5kCnRoZSBoYXJkd2FyZS1xdWlyayBleGNlcHRpb24uCgoq KllFUyoqCgogYXJjaC9yaXNjdi9LY29uZmlnLmVycmF0YSAgICAgICAgICAgICAgICAgICAgfCAx NCArKysrKysrKysrKysrKwogYXJjaC9yaXNjdi9lcnJhdGEvc2lmaXZlL2VycmF0YS5jICAgICAg ICAgICAgfCAyMCArKysrKysrKysrKysrKysrKysrKwogYXJjaC9yaXNjdi9pbmNsdWRlL2FzbS9l cnJhdGFfbGlzdF92ZW5kb3JzLmggfCAgMyArKy0KIGFyY2gvcmlzY3YvaW5jbHVkZS9hc20vaW5z bi1kZWYuaCAgICAgICAgICAgIHwgMTYgKysrKysrKysrKysrKy0tLQogNCBmaWxlcyBjaGFuZ2Vk LCA0OSBpbnNlcnRpb25zKCspLCA0IGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2FyY2gvcmlz Y3YvS2NvbmZpZy5lcnJhdGEgYi9hcmNoL3Jpc2N2L0tjb25maWcuZXJyYXRhCmluZGV4IDZmMjMw YWViZDQ5NjguLjY1ZDAwZmI5ZGI5ZDcgMTAwNjQ0Ci0tLSBhL2FyY2gvcmlzY3YvS2NvbmZpZy5l cnJhdGEKKysrIGIvYXJjaC9yaXNjdi9LY29uZmlnLmVycmF0YQpAQCAtOTUsNiArOTUsMjAgQEAg Y29uZmlnIEVSUkFUQV9TVEFSRklWRV9KSDcxMDAKIAkgIFNheSAiWSIgaWYgeW91IHdhbnQgdG8g c3VwcG9ydCB0aGUgQmVhZ2xlViBTdGFybGlnaHQgYW5kL29yCiAJICBTdGFyRml2ZSBWaXNpb25G aXZlIFYxIGJvYXJkcy4KIAorY29uZmlnIEVSUkFUQV9TSUZJVkVfTUFMXzkwOTIKKwlib29sICJB cHBseSBTaUZpdmUgSExWL0hMVlgvSFNWIGZlbmNlIGVycmF0YSIKKwlkZXBlbmRzIG9uIEVSUkFU QV9TSUZJVkUgJiYgNjRCSVQKKwlkZWZhdWx0IHkKKwloZWxwCisJICBUaGlzIHdpbGwgYXBwbHkg dGhlIFNpRml2ZSBNQUwtOTA5MiBlcnJhdGEgdG8gYWRkIGZlbmNlLnJ3CisJICBpbnN0cnVjdGlv bnMgYXJvdW5kIGFsbCBITFYvSExWWC9IU1YgaW5zdHJ1Y3Rpb25zLgorCisJICBOb3RlOiBIU1RB VFVTLkhVIGlzIGNsZWFyZWQgZHVyaW5nIEtWTSBpbml0aWFsaXphdGlvbi4gSWYgZnV0dXJlCisJ ICBjaGFuZ2VzIGVuYWJsZSBIU1RBVFVTLkhVIHRvIGFsbG93IGh5cGVydmlzb3IgaW5zdHJ1Y3Rp b25zIGluCisJICBVLW1vZGUsIGFkZGl0aW9uYWwgZXJyYXRhIGhhbmRsaW5nIG1heSBiZSByZXF1 aXJlZC4KKworCSAgSWYgeW91IGRvbid0IGtub3cgd2hhdCB0byBkbyBoZXJlLCBzYXkgIlkiLgor CiBjb25maWcgRVJSQVRBX1RIRUFECiAJYm9vbCAiVC1IRUFEIGVycmF0YSIKIAlkZXBlbmRzIG9u IFJJU0NWX0FMVEVSTkFUSVZFCmRpZmYgLS1naXQgYS9hcmNoL3Jpc2N2L2VycmF0YS9zaWZpdmUv ZXJyYXRhLmMgYi9hcmNoL3Jpc2N2L2VycmF0YS9zaWZpdmUvZXJyYXRhLmMKaW5kZXggMzhhYWMy YzQ3ODQ1YS4uMzAyNWI5ZDY5NjZmOCAxMDA2NDQKLS0tIGEvYXJjaC9yaXNjdi9lcnJhdGEvc2lm aXZlL2VycmF0YS5jCisrKyBiL2FyY2gvcmlzY3YvZXJyYXRhL3NpZml2ZS9lcnJhdGEuYwpAQCAt NTEsNiArNTEsMjIgQEAgc3RhdGljIGJvb2wgZXJyYXRhX2NpcF8xMjAwX2NoZWNrX2Z1bmModW5z aWduZWQgbG9uZyAgYXJjaF9pZCwgdW5zaWduZWQgbG9uZyBpbXAKIAlyZXR1cm4gdHJ1ZTsKIH0K IAorc3RhdGljIGJvb2wgZXJyYXRhX21hbF85MDkyX2NoZWNrX2Z1bmModW5zaWduZWQgbG9uZyAg YXJjaF9pZCwgdW5zaWduZWQgbG9uZyBpbXBpZCkKK3sKKwkvKgorCSAqIEFmZmVjdGVkIGNvcmVz OgorCSAqIEFyY2hpdGVjdHVyZSBJRDogMHg4MDAwMDAwMDAwMDAwMTA5CisJICogSW1wbGVtZW50 YXRpb24gSUQ6IDB4MTkyNTEwMzEsIDB4MTkyNTEyMTcsIDB4MTkyNjAzMjAKKwkgKi8KKworCWlm IChhcmNoX2lkICE9IDB4ODAwMDAwMDAwMDAwMDEwOSkKKwkJcmV0dXJuIGZhbHNlOworCWlmIChp bXBpZCAhPSAweDE5MjUxMDMxICYmIGltcGlkICE9IDB4MTkyNTEyMTcgJiYgaW1waWQgIT0gMHgx OTI2MDMyMCkKKwkJcmV0dXJuIGZhbHNlOworCisJcmV0dXJuIHRydWU7Cit9CisKIHN0YXRpYyBz dHJ1Y3QgZXJyYXRhX2luZm9fdCBlcnJhdGFfbGlzdFtFUlJBVEFfU0lGSVZFX05VTUJFUl0gPSB7 CiAJewogCQkubmFtZSA9ICJjaXAtNDUzIiwKQEAgLTYwLDYgKzc2LDEwIEBAIHN0YXRpYyBzdHJ1 Y3QgZXJyYXRhX2luZm9fdCBlcnJhdGFfbGlzdFtFUlJBVEFfU0lGSVZFX05VTUJFUl0gPSB7CiAJ CS5uYW1lID0gImNpcC0xMjAwIiwKIAkJLmNoZWNrX2Z1bmMgPSBlcnJhdGFfY2lwXzEyMDBfY2hl Y2tfZnVuYwogCX0sCisJeworCQkubmFtZSA9ICJtYWwtOTA5MiIsCisJCS5jaGVja19mdW5jID0g ZXJyYXRhX21hbF85MDkyX2NoZWNrX2Z1bmMKKwl9LAogfTsKIAogc3RhdGljIHUzMiBfX2luaXRf b3JfbW9kdWxlIHNpZml2ZV9lcnJhdGFfcHJvYmUodW5zaWduZWQgbG9uZyBhcmNoaWQsCmRpZmYg LS1naXQgYS9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL2VycmF0YV9saXN0X3ZlbmRvcnMuaCBiL2Fy Y2gvcmlzY3YvaW5jbHVkZS9hc20vZXJyYXRhX2xpc3RfdmVuZG9ycy5oCmluZGV4IGVjN2ViYTM3 MzQzNzEuLmM2MmE4MmY2MDQ2OGEgMTAwNjQ0Ci0tLSBhL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20v ZXJyYXRhX2xpc3RfdmVuZG9ycy5oCisrKyBiL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vZXJyYXRh X2xpc3RfdmVuZG9ycy5oCkBAIC0xMSw3ICsxMSw4IEBACiAjaWZkZWYgQ09ORklHX0VSUkFUQV9T SUZJVkUKICNkZWZpbmUJRVJSQVRBX1NJRklWRV9DSVBfNDUzIDAKICNkZWZpbmUJRVJSQVRBX1NJ RklWRV9DSVBfMTIwMCAxCi0jZGVmaW5lCUVSUkFUQV9TSUZJVkVfTlVNQkVSIDIKKyNkZWZpbmUJ RVJSQVRBX1NJRklWRV9NQUxfOTA5MiAyCisjZGVmaW5lCUVSUkFUQV9TSUZJVkVfTlVNQkVSIDMK ICNlbmRpZgogCiAjaWZkZWYgQ09ORklHX0VSUkFUQV9USEVBRApkaWZmIC0tZ2l0IGEvYXJjaC9y aXNjdi9pbmNsdWRlL2FzbS9pbnNuLWRlZi5oIGIvYXJjaC9yaXNjdi9pbmNsdWRlL2FzbS9pbnNu LWRlZi5oCmluZGV4IGQyOWRhNmNjZDNkZDguLmIxYjk3ZWFiOTEwMDcgMTAwNjQ0Ci0tLSBhL2Fy Y2gvcmlzY3YvaW5jbHVkZS9hc20vaW5zbi1kZWYuaAorKysgYi9hcmNoL3Jpc2N2L2luY2x1ZGUv YXNtL2luc24tZGVmLmgKQEAgLTE5MSwxOCArMTkxLDI4IEBACiAJSU5TTl9SKE9QQ09ERV9TWVNU RU0sIEZVTkMzKDApLCBGVU5DNyg0OSksCQlcCiAJICAgICAgIF9fUkQoMCksIFJTMShnYWRkciks IFJTMih2bWlkKSkKIAorI2RlZmluZSBBTFRfU0lGSVZFX01BTF85MDkyX0ZFTkNFCQkJCQlcCitB TFRFUk5BVElWRSgibm9wIiwgImZlbmNlIHJ3LCBydyIsIFNJRklWRV9WRU5ET1JfSUQsCQkJXAor CSAgICBFUlJBVEFfU0lGSVZFX01BTF85MDkyLCBDT05GSUdfRVJSQVRBX1NJRklWRV9NQUxfOTA5 MikKKwogI2RlZmluZSBITFZYX0hVKGRlc3QsIGFkZHIpCQkJCQlcCisJQUxUX1NJRklWRV9NQUxf OTA5Ml9GRU5DRSAiXG4iCQkJCVwKIAlJTlNOX1IoT1BDT0RFX1NZU1RFTSwgRlVOQzMoNCksIEZV TkM3KDUwKSwJCVwKLQkgICAgICAgUkQoZGVzdCksIFJTMShhZGRyKSwgX19SUzIoMykpCisJICAg ICAgIFJEKGRlc3QpLCBSUzEoYWRkciksIF9fUlMyKDMpKSAiXG4iCQlcCisJQUxUX1NJRklWRV9N QUxfOTA5Ml9GRU5DRQogCiAjZGVmaW5lIEhMVl9XKGRlc3QsIGFkZHIpCQkJCQlcCisJQUxUX1NJ RklWRV9NQUxfOTA5Ml9GRU5DRSAiXG4iCQkJCVwKIAlJTlNOX1IoT1BDT0RFX1NZU1RFTSwgRlVO QzMoNCksIEZVTkM3KDUyKSwJCVwKLQkgICAgICAgUkQoZGVzdCksIFJTMShhZGRyKSwgX19SUzIo MCkpCisJICAgICAgIFJEKGRlc3QpLCBSUzEoYWRkciksIF9fUlMyKDApKSAiXG4iCQlcCisJQUxU X1NJRklWRV9NQUxfOTA5Ml9GRU5DRQogCiAjaWZkZWYgQ09ORklHXzY0QklUCiAjZGVmaW5lIEhM Vl9EKGRlc3QsIGFkZHIpCQkJCQlcCisJQUxUX1NJRklWRV9NQUxfOTA5Ml9GRU5DRSAiXG4iCQkJ CVwKIAlJTlNOX1IoT1BDT0RFX1NZU1RFTSwgRlVOQzMoNCksIEZVTkM3KDU0KSwJCVwKLQkgICAg ICAgUkQoZGVzdCksIFJTMShhZGRyKSwgX19SUzIoMCkpCisJICAgICAgIFJEKGRlc3QpLCBSUzEo YWRkciksIF9fUlMyKDApKSAiXG4iCQlcCisJQUxUX1NJRklWRV9NQUxfOTA5Ml9GRU5DRQogI2Vs c2UKICNkZWZpbmUgSExWX0QoZGVzdCwgYWRkcikJCQkJCVwKIAlfX0FTTV9TVFIoLmVycm9yICJo bHYuZCByZXF1aXJlcyA2NC1iaXQgc3VwcG9ydCIpCi0tIAoyLjUzLjAKCgpfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1yaXNjdiBtYWlsaW5nIGxp c3QKbGludXgtcmlzY3ZAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFk Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9CE75B22FC; Mon, 19 Oct 2026 14:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792418430; cv=none; b=m7t86ap7MwKh7GZOdewkcGXESifqsyW706VnCCxOgUsnK8ZbVll7gp6EaArIaG42QKhEIsYV2zEZO4je5D1lzVMnNiJI09CHeJr000BJn5UL2twbU1VYPdYpDN7+wcq0cWfXN93zF6AbIlbJv19fJsvsFocr4g+jKxV8uWVIJ9s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792418430; c=relaxed/simple; bh=HZyHm/8NGS5AjoFW9jMzeT2t1j7Hr38G0rq7hobWajo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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d0U/VQ0GecWNIUJECjX1xxjow9XWa3cVsxgVY/hZHS3sXU/RM1fRmz03pDpVC66OOa G4c8OUF8bJ3v31W3oMR9gSlN1t47EVuXi7yqN4NgLiFxdmjYjlzwlRQsoxBI/CnF7O 7MhfkTnCBtyHw== From: Sasha Levin To: patches@lists.linux.dev, stable@vger.kernel.org Cc: Yong-Xuan Wang , Samuel Holland , Paul Walmsley , Sasha Levin , palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH AUTOSEL 6.18] RISC-V: errata: Add SiFive MAL-9092 workaround Date: Mon, 19 Oct 2026 09:48:53 -0400 Message-ID: <20261019135441.1420968-242-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261019135441.1420968-1-sashal@kernel.org> References: <20261019135441.1420968-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.18.57 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Yong-Xuan Wang [ Upstream commit 148ab873d8194cb44f29474da3b4428fa2e100d1 ] SiFive cores with MAL-9092 require fence.rw instructions around HLV/HLVX/HSV hypervisor instructions to ensure proper memory ordering when accessing guest memory. Note that HSTATUS.HU is cleared during KVM initialization, restricting hypervisor instructions to HS-mode only. If future changes enable HSTATUS.HU for U-mode access, additional errata considerations will be needed. Signed-off-by: Yong-Xuan Wang Reviewed-by: Samuel Holland Link: https://patch.msgid.link/20260817-sifive-errata-v1-1-6a80f1a2743d@sifive.com Signed-off-by: Paul Walmsley Signed-off-by: Sasha Levin --- LLM Generated explanations, may be completely bogus: The local tree is **6.18.y** (`v6.18.57`). This SiFive MAL-9092 change is a hardware-errata workaround for KVM guest-memory accesses, and the code it patches is already in this series. =============================================================== PHASE 1: COMMIT MESSAGE FORENSICS =============================================================== **Step 1.1: PARSE THE SUBJECT LINE** Record: [subsystem: RISC-V errata/SiFive] [action verb: Add] [workaround for SiFive MAL-9092: `fence.rw` around HLV/HLVX/HSV] **Step 1.2: PARSE ALL COMMIT MESSAGE TAGS** Record: - No `Fixes:` tag (expected for this review queue) - No `Reported-by:` / `Tested-by:` / `Acked-by:` - `Reviewed-by: Samuel Holland ` (SiFive, same vendor) - `Link: https://patch.msgid.link/20260817-sifive- errata-v1-1-6a80f1a2743d@sifive.com` - `Signed-off-by: Yong-Xuan Wang ` (author, SiFive) - `Signed-off-by: Paul Walmsley ` (RISC-V arch maintainer) - No `Cc: stable@vger.kernel.org` (expected; not a negative signal) - Sasha Levin SOB ignored per instructions **Step 1.3: ANALYZE THE COMMIT BODY TEXT** Record: - [Bug] SiFive cores with MAL-9092 do not provide the required memory ordering around hypervisor load/store (`HLV`/`HLVX`/`HSV`) when touching guest memory. - [Symptom] Wrong/stale guest instruction or data observed by the host hypervisor (KVM unprivileged guest-memory access). Not a documented oops; it is an architecture-level ordering hole. - [Version] None stated. Paul queued it for v7.3-rc. Affected `mimpid` values look like 2025-10-31, 2025-12-17, and 2026-03-20 silicon. - [Root cause] Missing `fence.rw` around those hypervisor instructions on specific `marchid`/`mimpid` combinations. `HSTATUS.HU` is left clear in KVM setup, so the workaround is HS-mode only. **Step 1.4: DETECT HIDDEN BUG FIXES** Record: Not a disguised cleanup. It is an explicit hardware-errata workaround, which is a stable exception category (quirks/workarounds). =============================================================== PHASE 2: DIFF ANALYSIS - LINE BY LINE =============================================================== **Step 2.1: INVENTORY THE CHANGES** Record: - `arch/riscv/Kconfig.errata`: +14 (`CONFIG_ERRATA_SIFIVE_MAL_9092`, `depends on ERRATA_SIFIVE && 64BIT`, `default y`) - `arch/riscv/errata/sifive/errata.c`: +20 (`errata_mal_9092_check_func` + list entry) - `arch/riscv/include/asm/errata_list_vendors.h`: +2/-1 (`ERRATA_SIFIVE_MAL_9092 2`, `ERRATA_SIFIVE_NUMBER 3`) - `arch/riscv/include/asm/insn-def.h`: +13/-3 (ALTERNATIVE nop→`fence rw,rw` around `HLVX_HU`/`HLV_W`/`HLV_D`) - Total: **4 files, +49/-4**. Functions: `errata_mal_9092_check_func` (new), `errata_list[]` (extended), HLV macros. Scope: single-arch surgical errata, not a refactor. **Step 2.2: UNDERSTAND THE CODE FLOW CHANGE** Record: - Probe: previously only CIP-453/CIP-1200. After, `marchid==0x8000000000000109` and `mimpid` in `{0x19251031,0x19251217,0x19260320}` also set bit `ERRATA_SIFIVE_MAL_9092`. - HLV macros: previously a single hypervisor load. After, `nop` (or patched `fence rw,rw`) both before and after the instruction via the existing `ALTERNATIVE` framework. - Normal KVM path (`kvm_riscv_vcpu_unpriv_read`), not an error path. Unaffected CPUs keep `nop`. **Step 2.3: IDENTIFY THE BUG MECHANISM** Record: [category: hardware workaround / memory-ordering errata] [mechanism: SiFive MAL-9092 omits ordering around HS-mode guest-memory hypervisor ops; alternatives patch in `fence.rw` only on matching CPUs] No HSV macros exist in this tree; wrapping HLV/HLVX is the complete in- tree coverage. **Step 2.4: ASSESS THE FIX QUALITY** Record: Matches CIP-453/CIP-1200 style. CPU-ID gated, `default y`, reviewed by SiFive and queued by the arch maintainer. Regression risk is low: extra nops on other CPUs; fences only on listed IDs. Residual risks: `insn-def.h` relies on include order for `ALTERNATIVE`/`SIFIVE_VENDOR_ID`/`ERRATA_SIFIVE_MAL_9092`; `warn_miss_errata()` can warn at boot if KVM is not built-in because the only alternative sites are in KVM. =============================================================== PHASE 3: GIT HISTORY INVESTIGATION =============================================================== **Step 3.1: BLAME THE CHANGED LINES** Record: HLV macros come from `26b73f14933e9c` (2022-10-02, “riscv: KVM: Apply insn-def to hlv encodings”). SiFive errata probe/list from `800149a77c2cb8` / `bff3ff525460b4` (2021, CIP-453/CIP-1200). The hypervisor accessors have been in tree for years; the errata is new silicon, not new kernel code. **Step 3.2: FOLLOW THE FIXES: TAG** Record: No `Fixes:` tag. The defect is in the CPU, not in a prior kernel commit. Not applicable. **Step 3.3: CHECK FILE HISTORY FOR RELATED CHANGES** Record: Recent `arch/riscv` errata work is MIPS P8700, T-Head GHOSTWRITE, vendor-header split (`16d18e3eaf29b`). None of those is a prerequisite for this patch. Standalone v1, not patch X/Y. **Step 3.4: CHECK THE AUTHOR'S OTHER COMMITS** Record: Yong-Xuan Wang is a SiFive contributor with RISC-V KVM work in this history (APLIC, Svade/Svadu). Samuel Holland (SiFive) reviewed. Not the arch maintainer; Paul Walmsley queued it. **Step 3.5: CHECK FOR DEPENDENT/PREREQUISITE COMMITS** Record: Needs RISC-V alternatives, `ERRATA_SIFIVE`, `errata_list_vendors.h`, and the HLV macros. All are ancestors of `v6.18.57` (`git merge-base --is-ancestor` succeeded for `16d18e3eaf29b` and `26b73f14933e9c`). Applies standalone. =============================================================== PHASE 4: MAILING LIST AND EXTERNAL RESEARCH =============================================================== **Step 4.1: FIND THE ORIGINAL PATCH DISCUSSION** Record: - `b4 dig -c f36eeaaaecc2c` → https://patch.msgid.link/20260817-sifive- errata-v1-1-6a80f1a2743d@sifive.com - `b4 dig -a`: **v1 only** (2026-08-17). No v2/v3. - Thread: patch + Paul Walmsley “Thanks, queued for v7.3-rc.” No NAKs, no stable nomination, no reviewer risk flags. - lore.kernel.org WebFetch returned 403; thread recovered via `b4 dig -m` mbox. **Step 4.2: CHECK WHO REVIEWED THE PATCH** Record: `b4 dig -w` To/Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Samuel Holland, other SiFive engineers, linux-riscv, linux-kernel. Appropriate RISC-V maintainers were on the patch. **Step 4.3: SEARCH FOR THE BUG REPORT** Record: No syzbot/bugzilla/user crash thread. This is a vendor errata from SiFive, not a fuzzer report. Public MAL-9092 documentation beyond the patch was not found. **Step 4.4: CHECK FOR RELATED PATCHES AND SERIES** Record: Single standalone patch (`[PATCH]`, not `[PATCH 1/N]`). No follow-ups on these files after this commit on HEAD. **Step 4.5: CHECK STABLE MAILING LIST HISTORY** Record: Web search of stable/MAL-9092 found no stable-list discussion and no stated reason to keep it out of stable. =============================================================== PHASE 5: CODE SEMANTIC ANALYSIS =============================================================== **Step 5.1: IDENTIFY KEY FUNCTIONS IN THE DIFF** Record: `errata_mal_9092_check_func` (new); `errata_list[]`; macros `ALT_SIFIVE_MAL_9092_FENCE`, `HLVX_HU`, `HLV_W`, `HLV_D`. Existing `sifive_errata_probe` / `sifive_errata_patch_func` pick it up via `ERRATA_SIFIVE_NUMBER`. **Step 5.2: TRACE CALLERS** Record: - `HLV*` used only in `arch/riscv/kvm/vcpu_exit.c` → `kvm_riscv_vcpu_unpriv_read()` - Callers of that: `kvm_riscv_vcpu_virtual_insn()` in `vcpu_insn.c` (guest insn fetch when `stval` is 0 / 16-bit); `vcpu_sbi_v01.c` (SBI 0.1 SEND_IPI / remote fence hart-mask reads) - Context: KVM VM-exit handling, not IRQ-entry core. Reachable whenever a guest traps. **Step 5.3: TRACE CALLEES** Record: Probe only compares `archid`/`impid`. Patching uses `patch_text_nosync` under `text_mutex`, same as CIP errata. Macros expand to `ALTERNATIVE("nop", "fence rw, rw", ...)`. **Step 5.4: FOLLOW THE CALL CHAIN** Record: Userspace QEMU/KVM on RISC-V → guest trap → `kvm_riscv_vcpu_unpriv_read` → HLV/HLVX. Unprivileged guest code can induce those exits. Only relevant with `CONFIG_KVM` on matching SiFive cores. **Step 5.5: SEARCH FOR SIMILAR PATTERNS** Record: Same pattern as CIP-453 and CIP-1200 in this tree. No HSV macros in `arch/riscv` at `v6.18.57` or HEAD, so nothing else to wrap here. =============================================================== PHASE 6: CROSS-REFERENCING AGAINST THE LOCAL TREE =============================================================== **Step 6.1: DOES THE BUGGY CODE EXIST IN THIS TREE?** Record: Yes. Local tree: `git describe HEAD` = `v6.18.57-155-gcdf239ca885b2`, `make kernelversion` = **6.18.57**. `git merge-base --is-ancestor f36eeaaaecc2c v6.18.57` failed (workaround not in 6.18.57). `v6.18.57` already has HLV macros in `insn-def.h`, KVM `vcpu_exit.c`, and SiFive errata with `ERRATA_SIFIVE_NUMBER 2`. The hardware bug is therefore live for matching CPUs running this series. **Step 6.2: CHECK FOR BACKPORT COMPLICATIONS** Record: `git diff --stat v6.18.57 f36eeaaaecc2c -- ` is exactly +49/-4. Clean apply. No conflicting refactor in 6.18.57 vs this patch. **Step 6.3: CHECK IF RELATED FIXES ARE ALREADY HERE** Record: `git log --grep=MAL-9092` only finds this candidate. No earlier equivalent workaround. =============================================================== PHASE 7: SUBSYSTEM AND MAINTAINER CONTEXT =============================================================== **Step 7.1: IDENTIFY THE SUBSYSTEM AND ITS CRITICALITY** Record: [arch/riscv errata + KVM guest-memory access] [IMPORTANT, not CORE: RISC-V-specific, and only listed SiFive cores with KVM]. Wrong guest-memory ordering is still a real virt correctness issue for those systems. **Step 7.2: ASSESS SUBSYSTEM ACTIVITY** Record: RISC-V errata and KVM are actively maintained. This is new- silicon errata on a mature HLV/KVM path, not a rewrite of a brand-new subsystem. =============================================================== PHASE 8: IMPACT AND RISK ASSESSMENT =============================================================== **Step 8.1: DETERMINE WHO IS AFFECTED** Record: RISC-V + `CONFIG_ERRATA_SIFIVE` (selected by `ARCH_SIFIVE`) + `CONFIG_64BIT` + KVM + `marchid 0x8000000000000109` with one of three `mimpid`s. Driver/platform-specific, not universal. **Step 8.2: DETERMINE THE TRIGGER CONDITIONS** Record: Trigger is KVM using HLV/HLVX to read guest memory (instruction emulate, SBI 0.1 hart masks). Common for any VM on those cores. Guest (typically unprivileged) can cause the VM-exit. Not a rare error-path- only bug. **Step 8.3: DETERMINE THE FAILURE MODE SEVERITY** Record: [Failure mode: missing memory fence → stale/wrong guest insn or data in the hypervisor] [Severity: HIGH — guest corruption or incorrect emulation; not a documented host panic]. Silent wrongness is worse than a WARN. **Step 8.4: CALCULATE RISK-BENEFIT RATIO** Record: - Benefit: HIGH for KVM on the listed SiFive cores (correct guest-memory access). - Risk: LOW — ~50 lines, ID-gated alternatives, same mechanism as CIP-1200 already in 6.18.57. Unaffected CPUs only gain nops. - Ratio: benefit outweighs risk for this 6.18.y tree. =============================================================== PHASE 9: FINAL SYNTHESIS =============================================================== **Step 9.1: COMPILE THE EVIDENCE** FOR: - Hardware errata/quirk, which stable explicitly accepts - Real KVM guest-memory ordering bug on shipping/soon-shipping SiFive cores - Small (+49/-4), uses existing alternatives/errata machinery - HLV/KVM/SiFive errata all present in 6.18.57; applies cleanly - Reviewed by SiFive, queued by RISC-V arch maintainer, no NAKs - CPU-ID match so other RISC-V systems are not functionally changed AGAINST: - New Kconfig symbol (standard for RISC-V errata, `default y`) - No field crash/syzbot report (vendor errata, typical) - Possible `warn_miss_errata` noise if KVM is disabled on an affected CPU - HSV mentioned in text but no HSV macros here (not a functional gap in 6.18.y) UNRESOLVED: - Public MAL-9092 datasheet text was not found (only the kernel patch) - lore.kernel.org HTTP 403; discussion recovered from b4 mbox instead **Step 9.2: APPLY THE STABLE RULES CHECKLIST** 1. Obviously correct and tested? **PASS** — ID-gated alternative fences; SiFive review; maintainer queued for 7.3-rc 2. Fixes a real bug that affects users? **PASS** — KVM guest-memory ordering on listed cores 3. Important issue? **PASS** — HIGH: incorrect hypervisor guest instruction/data reads (corruption / bad emulation) 4. Small and contained? **PASS** — 4 files, +49/-4 5. No new features or APIs? **PASS** — no userspace ABI; Kconfig is the usual errata toggle 6. Can apply to the local tree? **PASS** — clean vs `v6.18.57` **Step 9.3: CHECK FOR EXCEPTION CATEGORIES** Record: Hardware quirk/workaround (SiFive CPU errata), same class as USB/PCI quirks and existing CIP-453/CIP-1200. **Step 9.4: DECISION** This belongs on **this** 6.18.y tree. The HLV path has been here since 2022; 6.18.57 just lacks the fence workaround. LTS users who run KVM on these SiFive cores get a contained, ID-gated fix with the same shape as errata already in the series. Verification: - [Phase 1] Parsed tags: Reviewed-by Samuel Holland; Link to msgid 20260817-sifive-errata-v1-1; SOB Yong-Xuan Wang and Paul Walmsley; no Fixes/Reported-by/Cc:stable - [Phase 2] Diff: +49/-4 across Kconfig.errata, errata.c, errata_list_vendors.h, insn-def.h; ALTERNATIVE nop→fence around HLVX_HU/HLV_W/HLV_D - [Phase 3] git blame v6.18.57 insn-def.h: HLV macros from 26b73f14933e9c (2022); errata framework from 2021 CIP commits - [Phase 3] No Fixes: tag; standalone, not a series - [Phase 3] git merge-base --is-ancestor 26b73f14933e9c v6.18.57 → yes; 16d18e3eaf29b v6.18.57 → yes - [Phase 4] b4 dig -c f36eeaaaecc2c: lore URL found; -a: v1 only; -w: RISC-V maintainers on To/Cc; mbox: Paul “queued for v7.3-rc”; no NAK - [Phase 4] lore WebFetch 403; mbox used instead - [Phase 5] HLV* only used in kvm/vcpu_exit.c; callers vcpu_insn.c and vcpu_sbi_v01.c; git grep HSV_ in arch/riscv: none - [Phase 6] git describe HEAD: v6.18.57-155-gcdf239ca885b2; kernelversion 6.18.57 - [Phase 6] git merge-base --is-ancestor f36eeaaaecc2c v6.18.57 → not in 6.18.57; git grep MAL-9092 v6.18.57 → none - [Phase 6] git diff --stat v6.18.57 f36eeaaaecc2c -- the four files → exact patch, clean apply - [Phase 7] ARCH_SIFIVE selects ERRATA_SIFIVE; KVM is arch/riscv/kvm/Kconfig - [Phase 8] Failure mode: missing fence → wrong guest memory in KVM, severity HIGH - UNVERIFIED: full public MAL-9092 silicon manual; compile of vcpu_exit.c was inferred from include order, not by building The workaround is small, ID-gated, and fixes a real KVM memory-ordering erratum on hardware that 6.18.y can boot. It meets the stable rules and the hardware-quirk exception. **YES** arch/riscv/Kconfig.errata | 14 ++++++++++++++ arch/riscv/errata/sifive/errata.c | 20 ++++++++++++++++++++ arch/riscv/include/asm/errata_list_vendors.h | 3 ++- arch/riscv/include/asm/insn-def.h | 16 +++++++++++++--- 4 files changed, 49 insertions(+), 4 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 6f230aebd4968..65d00fb9db9d7 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -95,6 +95,20 @@ config ERRATA_STARFIVE_JH7100 Say "Y" if you want to support the BeagleV Starlight and/or StarFive VisionFive V1 boards. +config ERRATA_SIFIVE_MAL_9092 + bool "Apply SiFive HLV/HLVX/HSV fence errata" + depends on ERRATA_SIFIVE && 64BIT + default y + help + This will apply the SiFive MAL-9092 errata to add fence.rw + instructions around all HLV/HLVX/HSV instructions. + + Note: HSTATUS.HU is cleared during KVM initialization. If future + changes enable HSTATUS.HU to allow hypervisor instructions in + U-mode, additional errata handling may be required. + + If you don't know what to do here, say "Y". + config ERRATA_THEAD bool "T-HEAD errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c index 38aac2c47845a..3025b9d6966f8 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -51,6 +51,22 @@ static bool errata_cip_1200_check_func(unsigned long arch_id, unsigned long imp return true; } +static bool errata_mal_9092_check_func(unsigned long arch_id, unsigned long impid) +{ + /* + * Affected cores: + * Architecture ID: 0x8000000000000109 + * Implementation ID: 0x19251031, 0x19251217, 0x19260320 + */ + + if (arch_id != 0x8000000000000109) + return false; + if (impid != 0x19251031 && impid != 0x19251217 && impid != 0x19260320) + return false; + + return true; +} + static struct errata_info_t errata_list[ERRATA_SIFIVE_NUMBER] = { { .name = "cip-453", @@ -60,6 +76,10 @@ static struct errata_info_t errata_list[ERRATA_SIFIVE_NUMBER] = { .name = "cip-1200", .check_func = errata_cip_1200_check_func }, + { + .name = "mal-9092", + .check_func = errata_mal_9092_check_func + }, }; static u32 __init_or_module sifive_errata_probe(unsigned long archid, diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h index ec7eba3734371..c62a82f60468a 100644 --- a/arch/riscv/include/asm/errata_list_vendors.h +++ b/arch/riscv/include/asm/errata_list_vendors.h @@ -11,7 +11,8 @@ #ifdef CONFIG_ERRATA_SIFIVE #define ERRATA_SIFIVE_CIP_453 0 #define ERRATA_SIFIVE_CIP_1200 1 -#define ERRATA_SIFIVE_NUMBER 2 +#define ERRATA_SIFIVE_MAL_9092 2 +#define ERRATA_SIFIVE_NUMBER 3 #endif #ifdef CONFIG_ERRATA_THEAD diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index d29da6ccd3dd8..b1b97eab91007 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -191,18 +191,28 @@ INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \ __RD(0), RS1(gaddr), RS2(vmid)) +#define ALT_SIFIVE_MAL_9092_FENCE \ +ALTERNATIVE("nop", "fence rw, rw", SIFIVE_VENDOR_ID, \ + ERRATA_SIFIVE_MAL_9092, CONFIG_ERRATA_SIFIVE_MAL_9092) + #define HLVX_HU(dest, addr) \ + ALT_SIFIVE_MAL_9092_FENCE "\n" \ INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(50), \ - RD(dest), RS1(addr), __RS2(3)) + RD(dest), RS1(addr), __RS2(3)) "\n" \ + ALT_SIFIVE_MAL_9092_FENCE #define HLV_W(dest, addr) \ + ALT_SIFIVE_MAL_9092_FENCE "\n" \ INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(52), \ - RD(dest), RS1(addr), __RS2(0)) + RD(dest), RS1(addr), __RS2(0)) "\n" \ + ALT_SIFIVE_MAL_9092_FENCE #ifdef CONFIG_64BIT #define HLV_D(dest, addr) \ + ALT_SIFIVE_MAL_9092_FENCE "\n" \ INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(54), \ - RD(dest), RS1(addr), __RS2(0)) + RD(dest), RS1(addr), __RS2(0)) "\n" \ + ALT_SIFIVE_MAL_9092_FENCE #else #define HLV_D(dest, addr) \ __ASM_STR(.error "hlv.d requires 64-bit support") -- 2.53.0