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Mon, 19 Oct 2026 09:17:50 -0700 (PDT) Received: from redducc.localdomain ([183.83.156.125]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-360819be413sm33410985eec.13.2026.10.19.09.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 09:17:50 -0700 (PDT) From: redducc To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Vinod Koul , Vladimir Zapolskiy Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] clk: qcom: gcc-sm8450: Parent the eUSB3 clkref to bi_tcxo Date: Mon, 19 Oct 2026 16:17:38 +0000 Message-ID: <20261019161740.2384-2-sushmit718@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261019161740.2384-1-sushmit718@gmail.com> References: <20261019161740.2384-1-sushmit718@gmail.com> X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit gcc_eusb3_0_clkref_en gates the XO reference to the eUSB2 PHY, but it has no parent, so its rate reads as 0. On SM8475 the SNPS eUSB2 PHY takes this clock as its reference and rejects a 0 Hz rate as unsupported, so USB doesn't probe. Parent it to bi_tcxo, as tcsrcc-sm8550 does for its clkref branches. Fixes: db0c944ee92b ("clk: qcom: Add clock driver for SM8450") Assisted-by: LLM Signed-off-by: redducc --- drivers/clk/qcom/gcc-sm8450.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index cdae5d9c8aec..56503a45b64e 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -1500,6 +1500,10 @@ static struct clk_branch gcc_eusb3_0_clkref_en = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_eusb3_0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, -- 2.43.0