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Mon, 19 Oct 2026 11:06:08 -0700 (PDT) Received: from medusa.lab.kspace.sh ([208.88.152.253]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-89f57653ea9sm4184034b3a.32.2026.10.19.11.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 11:06:08 -0700 (PDT) Date: Mon, 19 Oct 2026 11:06:04 -0700 From: Mohamed Khalfella To: Daniel Wagner Cc: Keith Busch , Jens Axboe , Christoph Hellwig , Sagi Grimberg , Justin Tee , Naresh Gottumukkala , Paul Ely , Hannes Reinecke , Chaitanya Kulkarni , James Smart , Randy Jennings , linux-nvme@lists.infradead.org, linux-kernel@vger.kernel.org, Hannes Reinecke Subject: Re: [PATCH v6 01/18] nvmet: Rapid Path Failure Recovery set controller identify fields Message-ID: <20261019180604.GJ2931-mkhalfella@purestorage.com> References: <20260920182936.2317916-1-mkhalfella@purestorage.com> <20260920182936.2317916-2-mkhalfella@purestorage.com> <179206908475.1897932.6636243827945983905.b4-review@b4> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <179206908475.1897932.6636243827945983905.b4-review@b4> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261019_110610_936237_B9B26BA3 X-CRM114-Status: GOOD ( 16.69 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-nvme@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-nvme" X-Spam-Status: No, score=-16.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu 2026-10-15 14:58:04 +0200, Daniel Wagner wrote: > > maximum number of in-progress controller reset operations. CCRL is > > hardcoded to 4 as recommended by TP8028. > > The spec says at least 4. - CCRL (Cross-Controller Reset Limit): is an 8bit value that defines the maximum number of in-progress controller reset operations. CCRL is hardcoded to 4 because TP8028 recommended a value no less than 4. Right, I updated the commit message to mention that recommendation. > > > @@ -1695,6 +1699,11 @@ struct nvmet_ctrl *nvmet_alloc_ctrl(struct nvmet_alloc_ctrl_args *args) > > } > > ctrl->cntlid = ret; > > > > + if (!nvmet_is_disc_subsys(ctrl->subsys)) { > > + ctrl->ciu = get_random_u8() ? : 1; > > + ctrl->cirn = get_random_u64(); > > While get_random_u64 is very unlikely to return 0, it still possible, thus > > get_random_u64() ? : 1; Good point. Updated. > > would be the safe choice. Besides this nitpicking: > > Reviewed-by: Daniel Wagner > > -- > Daniel Wagner