From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=198.175.65.16 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1792443058; b=VUU0l4n+UgO4VOxmBT5fKok5W7UduNDmmjm63wYRLQJkBzuYnURG0HRo9ENLMV+n3paF Vuzj+ebvX6unQfPt2RkPmnMXErSNdgMEwjT9cl3TCua5oe3jgx5Fh0fqb8vzNB2mfg2en aimu9+OcYKEU35kzOtcneibayAkqhqtImvACjq/3UWbIH9/7xBl8s4nBdhOX5qzP6VtOy qAuzaXF1BIWBx6VobrTgpn+7web9eDyXJeIGfI8D3knaYn++lIBoloYtlt175Ioafj0W4 Hj/5A3sDBlMWaBzJZcvrZuCn6/hg60pb/dy2cwJKBvS37HjkAEgwJKntUdVRzFgtPoA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1792443058; h=DMARC-Filter:DKIM-Signature:X-CSE-ConnectionGUID:X-CSE-MsgGUID: X-IronPort-AV:X-IronPort-AV:Received:X-CSE-ConnectionGUID: X-CSE-MsgGUID:X-ExtLoop1:X-IronPort-AV:Received:From:To:Cc:Subject: Date:Message-ID:X-Mailer:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding; bh=CaWuUKCLnDkY1goQ4qPQ732xwjLW6llx4MJoHFMDOCc=; b=a0lCsLRuQMakFKkmvclLmK2/KQSXRL+hCvf83rLBbKpNlcG6lUa91Jlc+hMTRvcw/itO hOAYWAynT6uGjxN2SykEecvFmaiAZDanwRf+WMDG+2rinpJItUuBI1FfDGS1JLdMON9Nm 7j4ZaFYrOsI3YPwqyaXnQRQwo1HWmYvEdCBjY/MfialxwuFs/KAtaCSiq3tOnqLzbTLe1 T8pYjztOV+DfH3Ys+u5/bdg9niraq8UqhC/NOcz5e/Ip0Q2ebWAK9uxAv3SIAlaj+U9AO an6eHLvEcYt4gqBTbouKL2P86Sn26Fi50ylsEB8yNWCNTpEQ3k3kNIPdJ3sG5fw93OA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=GM1Ib29B; arc=none smtp.remote-ip=198.175.65.16 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 756E7606A31C for ; Mon, 19 Oct 2026 20:50:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 756E7606A31C Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=GM1Ib29B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1792443052; x=1823979052; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E1DGaniKkHlUROpMqW4y0ZxxqRsXPH56KuSd/JrAwLk=; b=GM1Ib29BaVIGDnb/Jo+nhuaii6rO0/ItJ61id4Vd4/xddNgbkrQFj+sx a/0s6IdvSna83dKi3WmG2lIsnSmhNVU/q4vkfRDPlV7j1wDvk2pOeueSG 7I588fP55s2j5PJrRX/if+nAJkfhoizjHf6s5Cb8kIX00yoJTurZS8Kmd rjZpN4eoe7f5m1YvlcX5zZu0PYpAf8zcIbpdcVuhKiQ/sWbdjm1FPW+Y3 Vyelr7lUihX3XvYOVI85ET0qIv/S8XQY12n3KysiSgyJj8jabKD7ZNEAm 3JU5JfgLD2b0dA4bls51PtQ0gZXT3KN8mkMsBEwlpFbeeV8vR6uZJHZl5 A==; X-CSE-ConnectionGUID: Ifo+SnFkTh6H2keUZ0O3ow== X-CSE-MsgGUID: /z7EiMesSiu/Pa+4Pii3MQ== X-IronPort-AV: E=McAfee;i="6800,10657,11940"; a="1131145" X-IronPort-AV: E=Sophos;i="6.27,168,1787036400"; d="scan'208";a="1131145" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2026 13:50:48 -0700 X-CSE-ConnectionGUID: ZQnfnfJPS1qbKytlPJ/Y3g== X-CSE-MsgGUID: hDn7FUBjRtqL+csoS3zdlQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,168,1787036400"; d="scan'208";a="3008632" Received: from spandruv-mobl5.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.220.87]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2026 13:50:49 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin , Chen Yu , David E Box , x86@kernel.org Cc: Christoph Hellwig , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck , "Borislav Petkov (AMD)" Subject: [PATCH v14 05/24] x86/resctrl: Delete resctrl_cpu_detect() Date: Mon, 19 Oct 2026 13:50:12 -0700 Message-ID: <20261019205031.16977-6-tony.luck@intel.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261019205031.16977-1-tony.luck@intel.com> References: <20261019205031.16977-1-tony.luck@intel.com> X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit resctrl now enumerates its monitoring properties itself, leaving the resctrl fields in cpuinfo_x86 without any consumers. These resctrl specific fields are populated from the vendor CPU identification paths. This unnecessarily placing resctrl details in generic x86 CPU setup. Delete the unused fields together with the code that populates them, removing resctrl from early CPU identification. Signed-off-by: Tony Luck Acked-by: Borislav Petkov (AMD) --- v14: Split first paragraph into two: context and problem. Don't list all the fields as a regex. --- arch/x86/include/asm/processor.h | 4 --- arch/x86/include/asm/resctrl.h | 3 --- arch/x86/kernel/cpu/amd.c | 3 --- arch/x86/kernel/cpu/hygon.c | 3 --- arch/x86/kernel/cpu/intel.c | 7 ----- arch/x86/kernel/cpu/resctrl/core.c | 42 ------------------------------ 6 files changed, 62 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index ec9db0dfa0df..4deb88c61c94 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -185,10 +185,6 @@ struct cpuinfo_x86 { /* in KB - valid for CPUS which support this call: */ unsigned int x86_cache_size; int x86_cache_alignment; /* In bytes */ - /* Cache QoS architectural values, valid only on the BSP: */ - int x86_cache_max_rmid; /* max index */ - int x86_cache_occ_scale; /* scale to bytes */ - int x86_cache_mbm_width_offset; int x86_power; unsigned long loops_per_jiffy; /* protected processor identification number */ diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h index c9f9db96f792..2031b30ff25b 100644 --- a/arch/x86/include/asm/resctrl.h +++ b/arch/x86/include/asm/resctrl.h @@ -193,12 +193,9 @@ static inline void resctrl_arch_mon_ctx_free(struct rdt_resource *r, enum resctrl_event_id evtid, void *ctx) { } -void resctrl_cpu_detect(struct cpuinfo_x86 *c); - #else static inline void resctrl_arch_sched_in(struct task_struct *tsk) {} -static inline void resctrl_cpu_detect(struct cpuinfo_x86 *c) {} #endif /* CONFIG_X86_CPU_RESCTRL */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 54e14ed276b5..dd82a11084f4 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -475,8 +474,6 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) } } - resctrl_cpu_detect(c); - /* Figure out Zen generations: */ switch (c->x86) { case 0x17: diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index ec51c2b9a257..0f226335dd9a 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "cpu.h" @@ -119,8 +118,6 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c) x86_amd_ls_cfg_ssbd_mask = 1ULL << 10; } } - - resctrl_cpu_detect(c); } static void early_init_hygon(struct cpuinfo_x86 *c) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 4297ceb2cb24..2f09710e863c 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include @@ -371,11 +370,6 @@ static void early_init_intel(struct cpuinfo_x86 *c) detect_tme_early(c); } -static void bsp_init_intel(struct cpuinfo_x86 *c) -{ - resctrl_cpu_detect(c); -} - #ifdef CONFIG_X86_32 /* * Early probe support logic for ppro memory erratum #50 @@ -804,7 +798,6 @@ static const struct cpu_dev intel_cpu_dev = { #endif .c_detect_tlb = intel_detect_tlb, .c_early_init = early_init_intel, - .c_bsp_init = bsp_init_intel, .c_init = init_intel, .c_x86_vendor = X86_VENDOR_INTEL, }; diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 82b27a0157ae..f0cfb37482d3 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -1083,48 +1083,6 @@ static __init void rdt_init_res_defs(void) static enum cpuhp_state rdt_online; -/* Runs once on the BSP during boot. */ -void resctrl_cpu_detect(struct cpuinfo_x86 *c) -{ - if (!cpu_has(c, X86_FEATURE_CQM_LLC) && !cpu_has(c, X86_FEATURE_ABMC)) { - c->x86_cache_max_rmid = -1; - c->x86_cache_occ_scale = -1; - c->x86_cache_mbm_width_offset = -1; - return; - } - - /* will be overridden if occupancy monitoring exists */ - c->x86_cache_max_rmid = cpuid_ebx(0xf); - - if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || - cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || - cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL) || - cpu_has(c, X86_FEATURE_ABMC)) { - u32 eax, ebx, ecx, edx; - - /* QoS sub-leaf, EAX=0Fh, ECX=1 */ - cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); - - c->x86_cache_max_rmid = ecx; - c->x86_cache_occ_scale = ebx; - c->x86_cache_mbm_width_offset = eax & 0xff; - - if (!c->x86_cache_mbm_width_offset) { - switch (c->x86_vendor) { - case X86_VENDOR_AMD: - c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD; - break; - case X86_VENDOR_HYGON: - c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_HYGON; - break; - default: - /* Leave c->x86_cache_mbm_width_offset as 0 */ - break; - } - } - } -} - static int __init resctrl_arch_late_init(void) { struct rdt_resource *r; -- 2.56.0