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Mon, 19 Oct 2026 15:28:57 -0700 (PDT) Received: from fabio-X870-EAGLE-WIFI7.tail2bb604.ts.net ([2804:1b3:a801:c1b3:7470:124f:adf9:af22]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-7cc7722e6fasm1303685137.7.2026.10.19.15.28.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 15:28:57 -0700 (PDT) From: Fabio Estevam To: broonie@kernel.org Cc: shengjiu.wang@gmail.com, linux-sound@vger.kernel.org, Fabio Estevam Subject: [PATCH 1/3] ASoC: fsl_sai: Defer TERE until stream setup Date: Mon, 19 Oct 2026 19:28:25 -0300 Message-ID: <20261019222827.131120-1-festevam@gmail.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On i.MX8MP, TERE also enables MCLK output. Runtime resume sets it before hw_params has configured the stream, so clocks can start from stale register values. In master mode, a custom board with a 400 MHz IPG clock drove BCLK at 200 MHz before hw_params rewrote xCR2. On first open, reset xCR4 also drove frame sync at about 100 MHz. Later opens can select the bus clock with DIV=0 and again drive BCLK prematurely. Enable TERE at the end of hw_params after programming stream format and clock settings. During runtime resume, restore TERE only when a configured stream is being resumed. Fixes: 3e4a82612998 ("ASoC: fsl_sai: MCLK bind with TX/RX enable bit") Signed-off-by: Fabio Estevam --- sound/soc/fsl/fsl_sai.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index d232c8f53061..51779d7f8bf8 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -799,6 +799,15 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~GENMASK_U32(min(channels, slots) - 1, 0)); + /* + * On i.MX8MP, TERE also enables the master clock output. Enable it + * after hw_params has configured the stream to avoid briefly driving + * clocks from stale register values. + */ + if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) + regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), + FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); + return 0; } @@ -1983,7 +1992,13 @@ static int fsl_sai_runtime_resume(struct device *dev) if (ret) goto disable_rx_clk; - if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) + /* + * A fresh stream has not configured its clock divider yet. Keep TERE + * disabled until hw_params in that case; an already configured stream + * needs it restored after a system suspend. + */ + if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && + sai->mclk_streams) regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); -- 2.43.0