From: Jonathan Cameron <jic23@kernel.org>
To: Alison Schofield <alison.schofield@intel.com>
Cc: dave@stgolabs.net, dave.jiang@intel.com,
vishal.l.verma@intel.com, iweiny@kernel.org,
ming.li@zohomail.com, icheng@nvidia.com,
linux-cxl@vger.kernel.org
Subject: Re: [PATCH v4 7/9] cxl/region: Factor out cxl_port_setup_decoder()
Date: Tue, 20 Oct 2026 02:26:24 +0100 [thread overview]
Message-ID: <20261020022624.3cc65948@jic23-hlaptop> (raw)
In-Reply-To: <77d38f529a6fdb26cad5e52ac8116854e2d62a7c.1792263750.git.alison.schofield@intel.com>
On Sat, 17 Oct 2026 12:28:53 -0700
Alison Schofield <alison.schofield@intel.com> wrote:
> Once cxl_switch_port_setup_targets() has calculated the interleave for a
> port's decoder, it either checks that interleave against the decoder
> settings found for an auto region, or checks the decoder's interleave
> capabilities and programs the decoder for a user created region. Both paths
> are open coded in cxl_switch_port_setup_targets().
>
> Move both paths to a new helper, cxl_port_setup_decoder().
>
> No functional change.
>
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
given my feedback on v3 is now in the next patch.
> ---
> drivers/cxl/core/region.c | 88 ++++++++++++++++++++++-----------------
> 1 file changed, 50 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index d25df041e922..025cf21adfa9 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1565,46 +1565,11 @@ static int cxl_port_calc_interleave(struct cxl_port *port, struct cxl_region *cx
> return 0;
> }
>
> -static int cxl_switch_port_setup_targets(struct cxl_switch_decoder *cxlsd,
> - struct cxl_region *cxlr,
> - struct cxl_endpoint_decoder *cxled)
> +static int cxl_port_setup_decoder(struct cxl_port *port, struct cxl_region *cxlr,
> + struct cxl_decoder *cxld, int iw, int ig)
> {
> - struct cxl_port *port = to_cxl_port(cxlsd->cxld.dev.parent);
> - int iw, ig, rc, pos = cxled->pos;
> - struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr);
> - struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> - struct cxl_ep *ep = cxl_ep_load(port, cxlmd);
> struct cxl_region_params *p = &cxlr->params;
> - struct cxl_decoder *cxld = &cxlsd->cxld;
> -
> - /*
> - * While root level decoders support x3, x6, x12, switch level
> - * decoders only support powers of 2 up to x16.
> - */
> - if (!is_power_of_2(cxl_rr->nr_targets)) {
> - dev_dbg(&cxlr->dev, "%s:%s: invalid target count %d\n",
> - dev_name(port->uport_dev), dev_name(&port->dev),
> - cxl_rr->nr_targets);
> - return -EINVAL;
> - }
> -
> - if (cxl_rr->nr_targets_set) {
> - for (int i = 0; i < cxl_rr->nr_targets_set; i++)
> - if (ep->dport == cxlsd->target[i]) {
> - int distance = cxl_port_peer_distance(port, cxlr);
> -
> - rc = check_last_peer(cxled, ep, cxl_rr,
> - distance);
> - if (rc)
> - return rc;
> - goto out_target_set;
> - }
> - goto add_target;
> - }
> -
> - rc = cxl_port_calc_interleave(port, cxlr, cxl_rr, &iw, &ig);
> - if (rc)
> - return rc;
> + int rc;
>
> if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) {
> if (cxld->interleave_ways != iw ||
> @@ -1643,6 +1608,53 @@ static int cxl_switch_port_setup_targets(struct cxl_switch_decoder *cxlsd,
> }
> dev_dbg(&cxlr->dev, "%s:%s iw: %d ig: %d\n", dev_name(port->uport_dev),
> dev_name(&port->dev), iw, ig);
> +
> + return 0;
> +}
> +
> +static int cxl_switch_port_setup_targets(struct cxl_switch_decoder *cxlsd,
> + struct cxl_region *cxlr,
> + struct cxl_endpoint_decoder *cxled)
> +{
> + struct cxl_port *port = to_cxl_port(cxlsd->cxld.dev.parent);
> + int iw, ig, rc, pos = cxled->pos;
> + struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr);
> + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> + struct cxl_ep *ep = cxl_ep_load(port, cxlmd);
> + struct cxl_decoder *cxld = &cxlsd->cxld;
> +
> + /*
> + * While root level decoders support x3, x6, x12, switch level
> + * decoders only support powers of 2 up to x16.
> + */
> + if (!is_power_of_2(cxl_rr->nr_targets)) {
> + dev_dbg(&cxlr->dev, "%s:%s: invalid target count %d\n",
> + dev_name(port->uport_dev), dev_name(&port->dev),
> + cxl_rr->nr_targets);
> + return -EINVAL;
> + }
> +
> + if (cxl_rr->nr_targets_set) {
> + for (int i = 0; i < cxl_rr->nr_targets_set; i++)
> + if (ep->dport == cxlsd->target[i]) {
> + int distance = cxl_port_peer_distance(port, cxlr);
> +
> + rc = check_last_peer(cxled, ep, cxl_rr,
> + distance);
> + if (rc)
> + return rc;
> + goto out_target_set;
> + }
> + goto add_target;
> + }
> +
> + rc = cxl_port_calc_interleave(port, cxlr, cxl_rr, &iw, &ig);
> + if (rc)
> + return rc;
> +
> + rc = cxl_port_setup_decoder(port, cxlr, cxld, iw, ig);
> + if (rc)
> + return rc;
> add_target:
> if (cxl_rr->nr_targets_set == cxl_rr->nr_targets) {
> dev_dbg(&cxlr->dev,
next prev parent reply other threads:[~2026-10-20 1:26 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-17 19:19 [PATCH v4 0/9] cxl/region: Refactor cxl_port_setup_targets() Alison Schofield
2026-10-17 19:19 ` [PATCH v4 1/9] cxl: Add interleave encoding validity helpers Alison Schofield
2026-10-17 19:19 ` [PATCH v4 2/9] cxl/region: Rename cxl_port_setup_targets() to cxl_switch_port_setup_targets() Alison Schofield
2026-10-17 19:19 ` [PATCH v4 3/9] cxl/region: Factor out cxl_port_peer_distance() Alison Schofield
2026-10-17 19:19 ` [PATCH v4 4/9] cxl/region: Calculate peer distance only for reused targets Alison Schofield
2026-10-19 7:31 ` Richard Cheng
2026-10-19 19:53 ` Alison Schofield
2026-10-20 1:24 ` Jonathan Cameron
2026-10-20 2:29 ` Li Ming
2026-10-17 19:19 ` [PATCH v4 5/9] cxl/region: Factor out cxl_port_parent_interleave() Alison Schofield
2026-10-17 19:19 ` [PATCH v4 6/9] cxl/region: Factor out cxl_port_calc_interleave() Alison Schofield
2026-10-17 19:28 ` [PATCH v4 7/9] cxl/region: Factor out cxl_port_setup_decoder() Alison Schofield
2026-10-20 1:26 ` Jonathan Cameron [this message]
2026-10-17 19:28 ` [PATCH v4 8/9] cxl/region: Simplify switch port target setup control flow Alison Schofield
2026-10-20 1:27 ` Jonathan Cameron
2026-10-20 2:33 ` Li Ming
2026-10-17 19:28 ` [PATCH v4 9/9] cxl/region: Factor out cxl_switch_port_add_target() Alison Schofield
2026-10-20 1:28 ` Jonathan Cameron
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