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Tue, 20 Oct 2026 14:31:16 +0000 Received: from CHBPR12MB731189.namprd12.prod.outlook.com ([fe80::b0e5:123d:fe06:e10d]) by CHBPR12MB731189.namprd12.prod.outlook.com ([fe80::b0e5:123d:fe06:e10d%6]) with mapi id 15.21.0546.012; Tue, 20 Oct 2026 14:31:16 +0000 Date: Tue, 20 Oct 2026 11:31:15 -0300 From: Jason Gunthorpe To: Christian =?utf-8?B?S8O2bmln?= Cc: Thomas =?utf-8?Q?Hellstr=C3=B6m?= , Alistair Popple , Karl Mehltretter , Dongwon Kim , dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org, iommu@lists.linux.dev, Kevin Tian , Leon Romanovsky , linaro-mm-sig@lists.linaro.org, linux-media@vger.kernel.org, Matthew Brost , Simona Vetter , Sumit Semwal , Vivek Kasireddy Subject: Re: [PATCH RFC 03/26] dma-buf: Add dma_buf_mapping_attach() Message-ID: <20261020143115.GE3008132@nvidia.com> References: <0-v1-b5cab63049c0+191af-dmabuf_map_type_jgg@nvidia.com> <3-v1-b5cab63049c0+191af-dmabuf_map_type_jgg@nvidia.com> <20261016202653.97339-1-kmehltretter@gmail.com> <8d4cb20b70ac4c3f36d8d631769757158af2ac8e.camel@linux.intel.com> <20261019133031.GQ13920@nvidia.com> <41bd4593-5918-4cda-922b-251805c25b60@amd.com> Content-Type: text/plain; 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Yeah, if ther is some value thing can be excluded right from the start. > > Further, I had the (perhaps naive) expectation that the interconnect > > option was not something that would change during mapping. I did not > > think you would loose your PCIe option if ualink becomes available, or > > vice versa. Though on deeper reflection I suppose someone could build > > HW so you might loose your ualink option if the dmabuf is moved to > > system memory while PCIe would still work. > > Yeah, that is definitely not correct. > > We have the clear requirement here that when one interconnect > physically fails that we can still do things like let the work reach > the next checkpoint, then it is taken of the HW, and the HW > suspended for repair, then resumed and then work can continue.... > > Similarly we have on the graphics side the requirement that physical > placement can be moved to system memory because of some other device > attaching, pinning for scanout or something suddenly requires the > backing store to be contiguously allocated etc,,, > > So there are vast requirements that a buffer changes location when > the mapping changes. I mean it is kind of pointless to have a > feature like ODP to suspend your traffic if the underlying physical > location of the memory can't change. At least here, I am not aware of anyone actually using the ODP capabilities to move and migrate memory. It seems by far and away the most common use case is permanently pin things. It seems like in these very complicated chips the placement of the memory is a critical decision, if it moves around the performance is so destroyed you may as well not bother. I know this is not everyone and every use case, but it has been a bit eye opening we built all this complex ODP stuf and I struggle to justify it with an actual real user. But yes, we should try to build it as you describe. Thanks, Jason