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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH01EPF000BE94A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6601 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Add a new option to the USERQ ioctl, which is called with the queue_id of an existing user queue and an unused queue_id, and changes that queue's id to the new value. Calling with an invalid new handle will fail. Calling with new_handle = handle will succeed if that queue exists but not do anything. Performing this operation on a queue with signals or waits outstanding is fine, as those hold not the queue_id but a direct reference to the queue object. v3: Poison queue and misc fixes v4: Using xas interface v5: Now with accompanying igt and criu changes Signed-off-by: David Francis --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 46 +++++++++++++++++++++++ include/uapi/drm/amdgpu_drm.h | 17 +++++++-- 2 files changed, 60 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 5aa53b2f4355..1310004ec63f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -852,6 +852,11 @@ static int amdgpu_userq_input_args_validate(struct drm_device *dev, break; case AMDGPU_USERQ_OP_LIST: break; + case AMDGPU_USERQ_OP_CHANGE_ID: + if (!args->change_in.new_queue_id || + args->change_in.new_queue_id > AMDGPU_MAX_USERQ_COUNT) + return -EINVAL; + break; default: return -EINVAL; } @@ -995,6 +1000,44 @@ amdgpu_userq_list(struct drm_file *filp, union drm_amdgpu_userq *args) return ret; } +static int amdgpu_userq_change_id(struct drm_file *filp, union drm_amdgpu_userq *args) +{ + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; + XA_STATE(xas, &uq_mgr->userq_xa, args->change_in.new_queue_id); + struct amdgpu_usermode_queue *queue; + int ret; + + if (args->change_in.new_queue_id == args->change_in.queue_id) + return -EINVAL; + + do { + xas_lock(&xas); + + queue = xa_load(&uq_mgr->userq_xa, args->change_in.queue_id); + if (!queue) { + ret = -EINVAL; + goto unlock; + } + + if (xas_load(&xas)) { + ret = -EBUSY; + goto unlock; + } + + xas_store(&xas, queue); + ret = xas_error(&xas); + if (ret) + goto unlock; + + __xa_erase(&uq_mgr->userq_xa, args->change_in.queue_id); +unlock: + xas_unlock(&xas); + } while (xas_nomem(&xas, GFP_KERNEL)); + + return ret; +} + bool amdgpu_userq_enabled(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); @@ -1041,6 +1084,9 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, case AMDGPU_USERQ_OP_LIST: r = amdgpu_userq_list(filp, args); break; + case AMDGPU_USERQ_OP_CHANGE_ID: + r = amdgpu_userq_change_id(filp, args); + break; default: drm_dbg_driver(dev, "Invalid user queue op specified: %d\n", args->in.op); return -EINVAL; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 92738d630eea..37d0efd1eda4 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -330,9 +330,10 @@ union drm_amdgpu_ctx { }; /* user queue IOCTL operations */ -#define AMDGPU_USERQ_OP_CREATE 1 -#define AMDGPU_USERQ_OP_FREE 2 -#define AMDGPU_USERQ_OP_LIST 3 +#define AMDGPU_USERQ_OP_CREATE 1 +#define AMDGPU_USERQ_OP_FREE 2 +#define AMDGPU_USERQ_OP_LIST 3 +#define AMDGPU_USERQ_OP_CHANGE_ID 4 /* queue priority levels */ /* low < normal low < normal high < high */ @@ -464,10 +465,20 @@ struct drm_amdgpu_userq_list_in_out { __u64 entries; }; +struct drm_amdgpu_userq_change_id_in { + /** AMDGPU_USERQ_OP_CHANGE_ID */ + __u32 op; + /** Queue id of some queue */ + __u32 queue_id; + /** Queue id to change that queue to */ + __u32 new_queue_id; +}; + union drm_amdgpu_userq { struct drm_amdgpu_userq_in in; struct drm_amdgpu_userq_out out; struct drm_amdgpu_userq_list_in_out list_in_out; + struct drm_amdgpu_userq_change_id_in change_in; }; /* GFX V11 IP specific MQD parameters */ -- 2.34.1