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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ad80cbe295sm906521a91.5.2026.10.20.13.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2026 13:47:49 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 03/12] drm/msm/a8xx: Add a8xx_aperture_acquire_slice() Date: Tue, 20 Oct 2026 13:46:17 -0700 Message-ID: <20261020204728.28844-4-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261020204728.28844-1-robin.clark@oss.qualcomm.com> References: <20261020204728.28844-1-robin.clark@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: SEeLjrzMH9Fy5yt8Q02Ee6H7loipTFk0 X-Proofpoint-ORIG-GUID: SEeLjrzMH9Fy5yt8Q02Ee6H7loipTFk0 X-Authority-Analysis: v=2.4 cv=EuJHPicA c=1 sm=1 tr=0 ts=6ad7d377 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=PjapJS5JrKSUkyaTbiQA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDA4MiBTYWx0ZWRfX3TakjthDLO8v qcqxdI+gyjBYExmxYFUb8k+G2JyWae0dpgG63d+TXB3Ul6OQJSyvavnyhuRvlLYRpKawgGiLHYE ci7+QW63uwtbhwKkN9wF2c6yE8K/x20= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDA4MiBTYWx0ZWRfX7zgtCuaTPYuZ hE5IEEL21R5mT/QkXnvdIywV7H+/coFCQFbWPmXfx/UWyC6h8cm6akDH8D8Jr7Zy6fc69DKUGf0 nzXONPBy+CZAhvqTfbBbYUY5iiHJqCoC+hcB+s5ti+2FwIfZoUs/PKqY6I118YpmAFCrSKiqLF5 IvAfJ2hQtUl5BKTlRndrA27xOaL87iG3NdABm75JY4Cb3bJinuDAzMBEimYXPYIjepK6zTcH2+f Q7A9apsc9cbKYn3H/oHIw1Sf6smWckd3p/4lD2mQvMU8CgFnrj9PZ4y1WCMrsOpk7RokAhAsxts iRzQekrv92wpuDWK/oPtjmHUK2v4IHQT+eVglvKM3DVo3YkegJm3uzGoI7/Mg6b/zm/R5nmHdnn 78XxTOXoPCgiPTDA/n2g37rx6l5lNZ7zHlMsa8UnmXCBg0jfePtSXHOMnkDNh8jdQowsu9dqfrP HAECN3ETehJcJobYxiA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_03,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 clxscore=1015 spamscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200082 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "dri-devel" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The gen8 snapshot code will need a bit more control. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 3 +++ drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 19 +++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index fb000b79fe2f..d60cbfaa0d8e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -348,6 +348,9 @@ void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); void a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring); int a6xx_zap_shader_init(struct msm_gpu *gpu); +void a8xx_aperture_acquire_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, + u32 slice, bool use_slice, + unsigned long *flags); void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags); void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags); void a8xx_aperture_clear(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index a14379e26fbe..72c84f73157a 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -16,7 +16,8 @@ #define GPU_PAS_ID 13 -static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) +static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, + u32 slice, bool use_slice) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); @@ -24,6 +25,9 @@ static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, val = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice); + if (use_slice) + val |= A8XX_CP_APERTURE_CNTL_HOST_USESLICEID; + if (a6xx_gpu->cached_aperture == val) return; @@ -32,14 +36,21 @@ static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, a6xx_gpu->cached_aperture = val; } -void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +void a8xx_aperture_acquire_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, + u32 slice, bool use_slice, + unsigned long *flags) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); - a8xx_aperture_slice_set(gpu, pipe, 0); + a8xx_aperture_slice_set(gpu, pipe, slice, use_slice); +} + +void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +{ + a8xx_aperture_acquire_slice(gpu, pipe, 0, false, flags); } void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) @@ -75,7 +86,7 @@ static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 u32 val; spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags); - a8xx_aperture_slice_set(gpu, pipe, slice); + a8xx_aperture_slice_set(gpu, pipe, slice, false); val = gpu_read(gpu, offset); spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags); -- 2.56.0