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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ad8035c42fsm1003438a91.17.2026.10.20.13.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2026 13:47:51 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 04/12] drm/msm/a8xx: Allow nonctx reglist to include GMU regs Date: Tue, 20 Oct 2026 13:46:18 -0700 Message-ID: <20261020204728.28844-5-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261020204728.28844-1-robin.clark@oss.qualcomm.com> References: <20261020204728.28844-1-robin.clark@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: YZJMY2nHEqyo6j1gGTA3-c7FhxTWq93r X-Proofpoint-ORIG-GUID: YZJMY2nHEqyo6j1gGTA3-c7FhxTWq93r X-Authority-Analysis: v=2.4 cv=EuJHPicA c=1 sm=1 tr=0 ts=6ad7d37a cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=cg0wMmP-TNBUvudz7-YA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDA4MiBTYWx0ZWRfX2wdqo2e7YLTq djP0ZDuwe4KlkVaX0BGD+8Ikka5OMqRw6kq4CuJTh8gPKLr+D9uqZcMO9ScrJ1yf/8JXBV/BiSq VuRyaNdlKATj4jRB5WEFqmEiT3w/hGM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDA4MiBTYWx0ZWRfX38kgQiNL38ZP 1o1b9l/ZCFJZJ5ObFVL4SmTWDkH0mvPoNu7ItmSiL7zVAONYFrflUhGse9mHwWPIS/FM50pVUjD 4u3dlo8FHVsMbBfC3ke9UHb8ECRyD1/ChVeSUC0mM2C726S+Q9uzmzj/X5By2j+59atZUYs2Q9K bNInH1idMu5u1b3llO8Jo0E5DUlOOjDS/ryuZ6EJF2s+xEhuWPYsX+Y439SSGtBmLzFZGOkeUKg OL4TF0x5PVA/nhQfXlJpysu3xQ/R/b5A8Jyt3V82bMNg7S2B6G3P2PHq58QTZ8ji85InlAGbdLh 5Uga/6XfFWYewJ33Lo8spLqnxVUCj6CmtHDv6dTQqCCOy/paZ1Z9/AeFl8cbGcVNVScTVrqvTRc 0zm8qu4E+gi8g/U7MTDm3426JUA2zFiqom0e0kkAANAbM/EWoaxPFRtY1Ek2MHLHrUcfeNSyjlP d8D4nx48GapcluQeNOA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_03,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 clxscore=1015 spamscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200082 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "dri-devel" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 >From hw PoV, it's all part of the GPU. But from dt perspective it is it's own device with a separate io space. So we need to detect this and direct writes to the correct place. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 72c84f73157a..3e22ef788f2d 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -376,6 +376,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; const struct a6xx_info *info = adreno_gpu->info->a6xx; const struct adreno_reglist_pipe *regs = info->nonctxt_reglist; unsigned int pipe_id, i; @@ -395,7 +396,11 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) *gmem_protect = regs[i].value; - gpu_write(gpu, regs[i].offset, regs[i].value); + if ((regs[i].offset << 2) >= gmu->mmio_offset) { + gmu_write(gmu, regs[i].offset, regs[i].value); + } else { + gpu_write(gpu, regs[i].offset, regs[i].value); + } } a8xx_aperture_release(gpu, flags); -- 2.56.0