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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ad8030226csm1079181a91.12.2026.10.20.13.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2026 13:47:53 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 05/12] drm/msm/a8xx: Stop getting GMEM_PROTECT from nonctx list Date: Tue, 20 Oct 2026 13:46:19 -0700 Message-ID: <20261020204728.28844-6-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261020204728.28844-1-robin.clark@oss.qualcomm.com> References: <20261020204728.28844-1-robin.clark@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: OYx1DjFVNH6Dn2OcPzJKVuMJKoY4pfSR X-Proofpoint-GUID: OYx1DjFVNH6Dn2OcPzJKVuMJKoY4pfSR X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDA4MiBTYWx0ZWRfX11asadXU84/D HlRzQbe7PIUUJDyZBtglyvosqEAraI+mRpkD9yKxdrIntsZVJknJCYcIu47kZklqKtPZR6DcvLI nKatRkIk9aHfKA2Xqy46G7oxAEXsBZk= X-Authority-Analysis: v=2.4 cv=R7aWitRX c=1 sm=1 tr=0 ts=6ad7d37a cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=b4MSL0WmfgirtTH71F4A:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDA4MiBTYWx0ZWRfX3VrrwnjSwqDr GREW/N6g+9IpcLRfeadH31Ks1aBRAn9j4GIIYQsg69NbSpQeClH2AG01R+h2K5ag8eG8Mv+ZDon OCf2ybG4lY9Z5PdJjsCW+yb2MeM2vFJno8if+W+tu6EBd6VhLBFvyYLiNDU2Dr267aGBrwzmCZl 5uEN6cM35UbZQUMmi+UCGjXBmO657dXoEyLPDETIWBjRnKCM3qucEV+o0EzxZg/mgs4tv9vuyFA tB1PtFekr98RXcYMEff1NuVv4nJImEohtyaZiUJ8FuRc5V2w+UWebirIe+DK64MWhYPU75mEYl6 83pN+L6y7vSfpomvIUrmJP6DliPnVweWkejzop8tIm+ZX+Yh/aX2DBl9gXUOb1ZZbgqi2Oh+1ET phjdl3pyjTa7SFfDWD1HppUyTdPpI+EmRyaO0TJPdI73SppRO5Ssk2l3w2Gpdg1eYS6uFjVQyoO 76Dhli9cH5MQRG81Ipw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_03,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 impostorscore=0 bulkscore=0 spamscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200082 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "dri-devel" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 We can just simplify things and calculate the value, instead of manually adding it to the nonctx list. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 3e22ef788f2d..6d7982a117f7 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -373,7 +373,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) hbb_lo << 1 | ubwc_mode); } -static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) +static void a8xx_nonctxt_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; @@ -393,9 +393,6 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) if (!(BIT(pipe_id) & regs[i].pipe)) continue; - if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) - *gmem_protect = regs[i].value; - if ((regs[i].offset << 2) >= gmu->mmio_offset) { gmu_write(gmu, regs[i].offset, regs[i].value); } else { @@ -641,7 +638,6 @@ static int hw_init(struct msm_gpu *gpu) struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; unsigned int pipe_id, i; - u32 gmem_protect = 0; u64 gmem_range_min; int ret; @@ -722,7 +718,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A8XX_UCHE_CLIENT_PF, BIT(7) | 0x1); - a8xx_nonctxt_config(gpu, &gmem_protect); + a8xx_nonctxt_config(gpu); /* Enable fault detection */ gpu_write(gpu, REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, BIT(30) | 0xcfffff); @@ -841,8 +837,8 @@ static int hw_init(struct msm_gpu *gpu) * GMEM_PROTECT register should be programmed after GPU is transitioned to * non-secure mode */ - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, gmem_protect); - WARN_ON(!gmem_protect); + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, + (adreno_gpu->info->gmem / SZ_4K) << 16); a8xx_aperture_clear(gpu); if (!a6xx_gpu->pwrup_reglist_emitted) { -- 2.56.0