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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1f2d85a9bsm131107235e9.15.2026.10.20.20.15.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Oct 2026 20:15:35 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 11/33] target/i386: Implement and register CPUClass::exception_name() Date: Wed, 21 Oct 2026 05:13:44 +0200 Message-ID: <20261021031407.24862-12-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com> References: <20261021031407.24862-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX9RSRHuZLBJ6j A/3t8eVgsFJVzG/J2/eq/rPhVng/EULV9r3yQiSNJFk9ilkhXH3mXhHYW0S0ikCBRaSKThv7V0G 0DUQ2JCbncZtO6fAJW1ERPGbhpd123klzy91D8ZZEXGevc9B8NVNIH5pj4KdxC8rtb524f/UI4y dJHmK79bjDRC2KA35NVhZBAVTirlFC2u3G5St3+o/asOWmY2tZ1tXBuWIplhX+GbGO6Ktq9ZZRK oyueoTvr47mv3J5zjTP7UodwqrfuXM7QZADCBQDyCFePeBFIqTcCd8VFniHTR2xPCxLdhGwYcvS wPRyeqe6YJzlfMxr0F1YCR3leYLXt7ijAbHvqJZiAsIyri5aeb0skeQlb+V29+GXCBlxsm3jjlr YOl1EGd5k8OyqEkV/yDndwhbLh5V9ciBmfjRT0/F/LCyRa67tklmnXO+AmTX9e7kkHzRNskdnus L1+91eRM3CvdDvCyDbA== X-Proofpoint-ORIG-GUID: jibH1qHEsyMgTlgJUOwXlGvkvyfRzLai X-Proofpoint-GUID: jibH1qHEsyMgTlgJUOwXlGvkvyfRzLai X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX/ApeOBqtcy0q ef7q0OG/67NET0daCnh06hLUX2DQ1hOHvM6+70eKdpInso9ZWYCiFBOEWGYfcqUiP0UC7Pkxddt Db4vguQmSs9YnBb3LKn4+bvyuMdr7yo= X-Authority-Analysis: v=2.4 cv=HL5WhYtv c=1 sm=1 tr=0 ts=6ad82e59 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=v-QDjpm2zyCjAj2l2PQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 impostorscore=0 clxscore=1015 phishscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210012 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Implement x86_exception_name() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve X86 exception codes to names. Use the new helper in check_exception() and do_interrupt_all(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/i386/cpu.h | 2 ++ target/i386/cpu.c | 30 ++++++++++++++++++++++++++++++ target/i386/tcg/excp_helper.c | 5 +++-- target/i386/tcg/seg_helper.c | 6 ++++-- 4 files changed, 39 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e7a88074c07..3945e90371b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1517,6 +1517,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define EXCP_SYSCALL 0x101 /* only for user emulation */ #define EXCP_VSYSCALL 0x102 /* only for user emulation */ +const char *x86_exception_name(int excp); + /* i386-specific interrupt pending bits. */ #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5da80ade70e..1013f98b5a7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9372,6 +9372,35 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) return false; } +const char *x86_exception_name(int excp) +{ + static const char * const excp_names[] = { + [EXCP00_DIVZ] = "DIV#0", + [EXCP01_DB] = "DB", + [EXCP02_NMI] = "NMI", + [EXCP03_INT3] = "INT3", + [EXCP04_INTO] = "INTO", + [EXCP05_BOUND] = "BOUND", + [EXCP06_ILLOP] = "ILLOP", + [EXCP07_PREX] = "PREX", + [EXCP08_DBLE] = "DBLE", + [EXCP09_XERR] = "XERR", + [EXCP0A_TSS] = "TSS", + [EXCP0B_NOSEG] = "NOSEG", + [EXCP0C_STACK] = "STACK", + [EXCP0D_GPF] = "GPF", + [EXCP0E_PAGE] = "PAGE", + [EXCP10_COPR] = "COPR", + [EXCP11_ALGN] = "ALGN", + [EXCP12_MCHK] = "MCHK", + [EXCP_VMEXIT] = "VMEXIT", + [EXCP_SYSCALL] = "SYSCALL", + [EXCP_VSYSCALL] = "VSYSCALL", + }; + + return ARRAY_ELEM_OR_NULL(excp_names, excp) ?: "unknown"; +} + static void x86_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs = CPU(obj); @@ -10946,6 +10975,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; cc->class_by_name = x86_cpu_class_by_name; + cc->exception_name = x86_exception_name; cc->list_cpus = x86_cpu_list; cc->parse_features = x86_cpu_parse_featurestr; cc->dump_state = x86_cpu_dump_state; diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index d6410d6fc11..3a38366d866 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -56,8 +56,9 @@ static int check_exception(CPUX86State *env, int intno, int *error_code, int second_contributory = intno == 0 || (intno >= 10 && intno <= 13); - qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x new 0x%x\n", - env->old_exception, intno); + qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x (%s) new 0x%x (%s)\n", + env->old_exception, x86_exception_name(env->old_exception), + intno, x86_exception_name(intno)); #if !defined(CONFIG_USER_ONLY) if (env->old_exception == EXCP08_DBLE) { diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index c89d97e022b..006a2ee9cc3 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1208,9 +1208,11 @@ void do_interrupt_all(X86CPU *cpu, int intno, int is_int, if ((env->cr[0] & CR0_PE_MASK)) { static int count; - qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx + qemu_log("%6d: v=%02x (%s) e=%04x i=%d" + " cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx, - count, intno, error_code, is_int, + count, intno, x86_exception_name(intno), + error_code, is_int, env->hflags & HF_CPL_MASK, env->segs[R_CS].selector, env->eip, (int)env->segs[R_CS].base + env->eip, -- 2.55.0