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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e25828caesm2312844f8f.29.2026.10.20.20.16.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Oct 2026 20:16:08 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 15/33] target/microblaze: Implement and register CPUClass::exception_name() Date: Wed, 21 Oct 2026 05:13:48 +0200 Message-ID: <20261021031407.24862-16-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com> References: <20261021031407.24862-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=aI5lOr9m c=1 sm=1 tr=0 ts=6ad82e79 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=_ZqrUhsafL45AmjA-XwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: l10dsau97M7TKIwXHdvu0_QRNOFFeV8S X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX72p1Em/7cj6k QjcLcJUn4Wym0NH4VwI7veFbF/coMpUo5uHZdIb/GWX9FqeEHf8+4SSK8JLgEeIGMlIalipCCUd WC2f+TBqOACSbrLG73CDYxaI1N2HCJyH1WzpClgKV+lDGLIm685FcKkCS8D83huYsEQspKRkqfz XtqpCXG3144Je3REpg7znVHMNslyVgMMrA7yb97kTlSR8zBeala/rKSrssQyjee2W0oBVRj3gY6 SSRi29CprzErXAL8uLx2bFVBm6R7SGSgwksUkgnxHVDVpzvsZHwupsV7k9nMeCDEjfyE+nRcqmz qOLKYLW42ZcRONzI/7dhodhC3YbGZTxZ3r1ihw2PxWESOXcWZkbQZIcoryN8j8EcjnYiOlR3VTK URHiVhi5Q6BGorcWIgn7/iIS2uxnH+5C70oWD2UZjMuAY4v+8HWCGxnEApAYRz0kwlgNO6EkuAs BWccRkneaU/GV7j26VQ== X-Proofpoint-GUID: l10dsau97M7TKIwXHdvu0_QRNOFFeV8S X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX4RmtHFg9WP9+ Uzh0G5bO3FFH8naaEZLuV9is46MlCb0nrXQRy06vAYxIhnWWQCwFHH7nDJLkbXhyuoluiTEM3vH hLUQaLicVI8bXhceVaIxsaCmWgwhKGM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210012 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Implement microblaze_exception_name() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve MicroBlaze exception codes to names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/microblaze/cpu.h | 2 ++ target/microblaze/cpu.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b9602f72b94..fc2783693e3 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -36,6 +36,8 @@ typedef struct CPUArchState CPUMBState; #define EXCP_HW_BREAK 4 #define EXCP_HW_EXCP 5 +const char *microblaze_exception_name(int excp); + /* MicroBlaze-specific interrupt pending bits. */ #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 389a5124b12..f64488d0a08 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -79,6 +79,19 @@ static const struct { /* If no specific version gets selected, default to the following. */ #define DEFAULT_CPU_VERSION "10.0" +const char *microblaze_exception_name(int excp) +{ + static const char * const excp_names[] = { + [EXCP_MMU] = "mmu", + [EXCP_IRQ] = "irq", + [EXCP_SYSCALL] = "syscall", + [EXCP_HW_BREAK] = "hw break", + [EXCP_HW_EXCP] = "hw excp", + }; + + return ARRAY_ELEM_OR_NULL(excp_names, excp) ?: "unknown"; +} + static void mb_cpu_set_pc(CPUState *cs, vaddr value) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); @@ -469,6 +482,7 @@ static void mb_cpu_class_init(ObjectClass *oc, const void *data) &mcc->parent_phases); cc->class_by_name = mb_cpu_class_by_name; + cc->exception_name = microblaze_exception_name; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; cc->get_pc = mb_cpu_get_pc; -- 2.55.0