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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1fcdd3855sm11075905e9.1.2026.10.20.20.17.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Oct 2026 20:17:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 22/33] target/riscv: Register CPUClass::exception_name() handler Date: Wed, 21 Oct 2026 05:13:55 +0200 Message-ID: <20261021031407.24862-23-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com> References: <20261021031407.24862-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=YuKa1IYX c=1 sm=1 tr=0 ts=6ad82eaf cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=y9j7XMdMAJhvWi9Kj2cA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfXw/5ww/bsazyD oZ8lp5Exc47+vq7Yw79JcMK04uC9i7xvmpti2zN3/mW25Bs1Z50wmY842iX3Hwv27nINdoYCZYh lbp6uxTlAzbpyIx71I3cjD65+z8Br3c= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX+iFf5Fe2DMk1 EAq2UIw5M4SkR7FZXxkH6gffR1tLZi9pNVNMKZtrkIuUc+eNz9R+zD0erYNExKYaATZhgZcEDBy Zl08AbzhQm+oUUa1HGzIpEvq0S+FP8l8TxUo6xrgkFmaa3l+L1lM3yS7rNgXAztrqrHJXdlDgcm 9r3LAfEnULvtJCA9syxxtd5A0oTXfVLtYpu5a/RhHN0V8hVi30XmbqRWOftHnBQQCmwRtkAK1R2 Vv5JrM1qZo5VeHQnL20Ci7htO3eboAWSB+2sOYyW0q7AnOcvVI0XQDWA8osFGPxtMnqiZUFSLFK V7/2JjCw1UqzM+AsZg2vs704ypdees+nzz81MTb8AYetbJU0bIWfx1naIGXoCI44Il896UFiEH/ CxQjKht8GfC3l5TTd0I3pw1jjpSWmwA6chk0ARhMaFn6SsjwYUGSuXWZyKsJEM539UmjgiiVnyz ATVTt0YoAgxhLWDy2fQ== X-Proofpoint-GUID: iV9-6oBi9B3Bg3mz4Cc_4TSpIV4xGO4B X-Proofpoint-ORIG-GUID: iV9-6oBi9B3Bg3mz4Cc_4TSpIV4xGO4B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 spamscore=0 clxscore=1015 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210012 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Factor riscv_excp_name() and riscv_intr_name() out of riscv_cpu_get_trap_name(). Register riscv_excp_name() as the CPUClass::exception_name() handler, so the common exception logging can resolve RISCV exception codes to names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 29 ++++++++++++++++++----------- target/riscv/tcg/op_helper.c | 2 +- 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b65d6319940..49a1186bdbb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -672,6 +672,7 @@ G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +const char *riscv_excp_name(int excp); char *riscv_isa_string(RISCVCPU *cpu); int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 08a4d14ea1f..9e9a9603685 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -398,6 +398,14 @@ static const char * const riscv_excp_names[] = { [RISCV_EXCP_SEMIHOST] = "semihost", }; +const char *riscv_excp_name(int excp) +{ + if ((excp < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[excp]) { + return riscv_excp_names[excp]; + } + return "unknown"; +} + static const char * const riscv_intr_names[] = { [IRQ_U_SOFT] = "u_software", [IRQ_S_SOFT] = "s_software", @@ -415,19 +423,17 @@ static const char * const riscv_intr_names[] = { [IRQ_PMU_OVF] = "counter_overflow", }; +static const char *riscv_intr_name(int intr) +{ + if ((intr < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[intr]) { + return riscv_intr_names[intr]; + } + return "unknown"; +} + const char *riscv_cpu_get_trap_name(uint64_t cause, bool async) { - if (async) { - if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) { - return riscv_intr_names[cause]; - } - } else { - if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) { - return riscv_excp_names[cause]; - } - } - - return "(unknown)"; + return async ? riscv_intr_name(cause) : riscv_excp_name(cause); } void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) @@ -3128,6 +3134,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data) &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name; + cc->exception_name = riscv_excp_name; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->get_pc = riscv_cpu_get_pc; diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index b8b3e43ccd5..f85f5cd83c9 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -41,7 +41,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, CPUState *cs = env_cpu(env); trace_riscv_exception(exception, - riscv_cpu_get_trap_name(exception, false), + riscv_excp_name(exception), env->pc); cs->exception_index = exception; -- 2.55.0