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Signed-off-by: Yonggang Luo Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/sh4/cpu.h | 21 +++++++++++++++ target/sh4/helper.c | 60 +++++++++++++++++++++--------------------- target/sh4/op_helper.c | 16 +++++------ 3 files changed, 59 insertions(+), 38 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 6984bb462fb..a1e9049b7be 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -135,6 +135,27 @@ typedef struct memory_content { struct memory_content *next; } memory_content; +/* Guest trap numbers. */ +enum { + SH4_EXCP_RESET = 0x000, + SH4_EXCP_MANUAL_RESET = 0x020, + SH4_EXCP_TLB_MISS = 0x040, + SH4_EXCP_DTLB_MISS_WRITE = 0x060, + SH4_EXCP_INITIAL_PAGE_WRITE = 0x080, + SH4_EXCP_TLB_VIOLATION = 0x0a0, + SH4_EXCP_DTLB_VIOLATION_WRITE = 0x0c0, + SH4_EXCP_ADDR_ERROR = 0x0e0, + SH4_EXCP_DATA_WRITE = 0x100, + SH4_EXCP_FPU = 0x120, + SH4_EXCP_TLB_MULTIPLE = 0x140, + SH4_EXCP_TRAPA = 0x160, + SH4_EXCP_ILLEGAL_INSTRUCTION = 0x180, + SH4_EXCP_SLOT_ILLEGAL_INSTRUCTION = 0x1a0, + SH4_EXCP_USER_BREAK = 0x1e0, + SH4_EXCP_FPU_DISABLE = 0x800, + SH4_EXCP_SLOT_FPU_DISABLE = 0x820, +}; + typedef struct CPUArchState { uint32_t flags; /* general execution flags */ uint32_t gregs[24]; /* general registers */ diff --git a/target/sh4/helper.c b/target/sh4/helper.c index b6b057f104b..0fbd613f333 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -70,7 +70,7 @@ void superh_cpu_do_interrupt(CPUState *cs) do_irq = do_irq && (cs->exception_index == -1); if (env->sr & (1u << SR_BL)) { - if (do_exp && cs->exception_index != 0x1e0) { + if (do_exp && cs->exception_index != SH4_EXCP_USER_BREAK) { /* In theory a masked exception generates a reset exception, which in turn jumps to the reset vector. However this only works when using a bootloader. When using a kernel and an @@ -97,43 +97,43 @@ void superh_cpu_do_interrupt(CPUState *cs) if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *expname; switch (cs->exception_index) { - case 0x0e0: + case SH4_EXCP_ADDR_ERROR: expname = "addr_error"; break; - case 0x040: + case SH4_EXCP_TLB_MISS: expname = "tlb_miss"; break; - case 0x0a0: + case SH4_EXCP_TLB_VIOLATION: expname = "tlb_violation"; break; - case 0x180: + case SH4_EXCP_ILLEGAL_INSTRUCTION: expname = "illegal_instruction"; break; - case 0x1a0: + case SH4_EXCP_SLOT_ILLEGAL_INSTRUCTION: expname = "slot_illegal_instruction"; break; - case 0x800: + case SH4_EXCP_FPU_DISABLE: expname = "fpu_disable"; break; - case 0x820: + case SH4_EXCP_SLOT_FPU_DISABLE: expname = "slot_fpu"; break; - case 0x100: + case SH4_EXCP_DATA_WRITE: expname = "data_write"; break; - case 0x060: + case SH4_EXCP_DTLB_MISS_WRITE: expname = "dtlb_miss_write"; break; - case 0x0c0: + case SH4_EXCP_DTLB_VIOLATION_WRITE: expname = "dtlb_violation_write"; break; - case 0x120: + case SH4_EXCP_FPU: expname = "fpu_exception"; break; - case 0x080: + case SH4_EXCP_INITIAL_PAGE_WRITE: expname = "initial_page_write"; break; - case 0x160: + case SH4_EXCP_TRAPA: expname = "trapa"; break; default: @@ -161,18 +161,18 @@ void superh_cpu_do_interrupt(CPUState *cs) if (do_exp) { env->expevt = cs->exception_index; switch (cs->exception_index) { - case 0x000: - case 0x020: - case 0x140: + case SH4_EXCP_RESET: + case SH4_EXCP_MANUAL_RESET: + case SH4_EXCP_TLB_MULTIPLE: env->sr &= ~(1u << SR_FD); env->sr |= 0xf << 4; /* IMASK */ env->pc = 0xa0000000; break; - case 0x040: - case 0x060: + case SH4_EXCP_TLB_MISS: + case SH4_EXCP_DTLB_MISS_WRITE: env->pc = env->vbr + 0x400; break; - case 0x160: + case SH4_EXCP_TRAPA: env->spc += 2; /* special case for TRAPA */ /* fall through */ default: @@ -632,7 +632,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, CPUState *cs = env_cpu(s); /* Multiple TLB Exception */ - cs->exception_index = 0x140; + cs->exception_index = SH4_EXCP_TLB_MULTIPLE; s->tea = addr; break; } @@ -828,33 +828,33 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, switch (ret) { case MMU_ITLB_MISS: case MMU_DTLB_MISS_READ: - cs->exception_index = 0x040; + cs->exception_index = SH4_EXCP_TLB_MISS; break; case MMU_DTLB_MULTIPLE: case MMU_ITLB_MULTIPLE: - cs->exception_index = 0x140; + cs->exception_index = SH4_EXCP_TLB_MULTIPLE; break; case MMU_ITLB_VIOLATION: - cs->exception_index = 0x0a0; + cs->exception_index = SH4_EXCP_TLB_VIOLATION; break; case MMU_DTLB_MISS_WRITE: - cs->exception_index = 0x060; + cs->exception_index = SH4_EXCP_DTLB_MISS_WRITE; break; case MMU_DTLB_INITIAL_WRITE: - cs->exception_index = 0x080; + cs->exception_index = SH4_EXCP_INITIAL_PAGE_WRITE; break; case MMU_DTLB_VIOLATION_READ: - cs->exception_index = 0x0a0; + cs->exception_index = SH4_EXCP_TLB_VIOLATION; break; case MMU_DTLB_VIOLATION_WRITE: - cs->exception_index = 0x0c0; + cs->exception_index = SH4_EXCP_DTLB_VIOLATION_WRITE; break; case MMU_IADDR_ERROR: case MMU_DADDR_ERROR_READ: - cs->exception_index = 0x0e0; + cs->exception_index = SH4_EXCP_ADDR_ERROR; break; case MMU_DADDR_ERROR_WRITE: - cs->exception_index = 0x100; + cs->exception_index = SH4_EXCP_DATA_WRITE; break; default: cpu_abort(cs, "Unhandled MMU fault"); diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 777380f8e40..8beac9ca034 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -33,10 +33,10 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: - cs->exception_index = 0x0e0; + cs->exception_index = SH4_EXCP_ADDR_ERROR; break; case MMU_DATA_STORE: - cs->exception_index = 0x100; + cs->exception_index = SH4_EXCP_DATA_WRITE; break; default: g_assert_not_reached(); @@ -67,22 +67,22 @@ void raise_exception(CPUSH4State *env, int index, void helper_raise_illegal_instruction(CPUSH4State *env) { - raise_exception(env, 0x180, 0); + raise_exception(env, SH4_EXCP_ILLEGAL_INSTRUCTION, 0); } void helper_raise_slot_illegal_instruction(CPUSH4State *env) { - raise_exception(env, 0x1a0, 0); + raise_exception(env, SH4_EXCP_SLOT_ILLEGAL_INSTRUCTION, 0); } void helper_raise_fpu_disable(CPUSH4State *env) { - raise_exception(env, 0x800, 0); + raise_exception(env, SH4_EXCP_FPU_DISABLE, 0); } void helper_raise_slot_fpu_disable(CPUSH4State *env) { - raise_exception(env, 0x820, 0); + raise_exception(env, SH4_EXCP_SLOT_FPU_DISABLE, 0); } void helper_sleep(CPUSH4State *env) @@ -97,7 +97,7 @@ void helper_sleep(CPUSH4State *env) void helper_trapa(CPUSH4State *env, uint32_t tra) { env->tra = tra << 2; - raise_exception(env, 0x160, 0); + raise_exception(env, SH4_EXCP_TRAPA, 0); } void helper_exclusive(CPUSH4State *env) @@ -255,7 +255,7 @@ static void update_fpscr(CPUSH4State *env, uintptr_t retaddr) cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT; if (cause & enable) { - raise_exception(env, 0x120, retaddr); + raise_exception(env, SH4_EXCP_FPU, retaddr); } } } -- 2.55.0