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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e254f0bc2sm2442908f8f.1.2026.10.20.20.17.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Oct 2026 20:17:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 28/33] target/sh4: Register CPUClass::exception_name() handler Date: Wed, 21 Oct 2026 05:14:01 +0200 Message-ID: <20261021031407.24862-29-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com> References: <20261021031407.24862-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX8EBnvIPff8br tI5MoNQa7z6erRNLn0RnrAfE5OFLcmMG0xkJ+ZFB5hODQGN/o1rLDuhIJ8nNIOHfWJhNB/A/rD2 hEGwdI7reQ6EyQXkVQRJGvmafTDTkVc= X-Proofpoint-ORIG-GUID: 1vsYwDGWXgzgB_Gajwuwb0ayo3UpY6JT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfXxSxP1CWc3qdY d8F9hQO3BMvEhJL4qxb5ANeiJRTmTbOFwtMMC8kyGzzVB684gCXmmUPr8jaBCDSzQLnmtapeUwd KUoHtpW9U3dPFdf5r6rU/k0untckOMysmK8teD7Kh3D8Hh6pU/hbqDyp1sEth26TebWHjkfhQtP 6T+zqwrOm2rl2JhrvFMqHR1Q1JLch8bbPbZwAJON5VhZTY3wbFn15aeFxvo7PwqZLaFDAuedR/W SRzAoczaCVC9PejuadRAfAm5QD9xQ4GV+cfETkFFAiulf0HPlvj7UCy8pmNItL/q3hnyliHRk3t DryLkPHQYsFguVO55N+bv0oZN+BBlu/VYUJagkX8nMVpFPJFy1JtqR71vFFpZ1xU2JFTNVh4cY4 gEbi1rRjVIF3+oUr8LT7jBU0Ep0ZCFno8jn+BjYY5D3dSosTdwjesRur8KmIjCWyZrnAFNCTVMM BX8fc1Txv2bYLF6wK9g== X-Authority-Analysis: v=2.4 cv=I6zw19gg c=1 sm=1 tr=0 ts=6ad82ee0 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=1bLhyRm5UWLPkFMrcSkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-GUID: 1vsYwDGWXgzgB_Gajwuwb0ayo3UpY6JT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 priorityscore=1501 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210012 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Factor sh4_exception_name() out of superh_cpu_do_interrupt() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve SH-4 exception codes to names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/sh4/cpu.h | 1 + target/sh4/cpu.c | 1 + target/sh4/helper.c | 101 +++++++++++++++++++++++--------------------- 3 files changed, 56 insertions(+), 47 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index a1e9049b7be..94f2f1278b9 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -258,6 +258,7 @@ struct SuperHCPUClass { uint32_t cvr; }; +const char *sh4_exception_name(int excp); void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 3bbdee301d5..97a718c3911 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -334,6 +334,7 @@ static void superh_cpu_class_init(ObjectClass *oc, const void *data) &scc->parent_phases); cc->class_by_name = superh_cpu_class_by_name; + cc->exception_name = sh4_exception_name; cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; cc->get_pc = superh_cpu_get_pc; diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 0fbd613f333..5856bab6983 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -47,6 +47,58 @@ #define MMU_DADDR_ERROR_READ (-12) #define MMU_DADDR_ERROR_WRITE (-13) +const char *sh4_exception_name(int excp) +{ + const char *name; + + switch (excp) { + case SH4_EXCP_ADDR_ERROR: + name = "addr_error"; + break; + case SH4_EXCP_TLB_MISS: + name = "tlb_miss"; + break; + case SH4_EXCP_TLB_VIOLATION: + name = "tlb_violation"; + break; + case SH4_EXCP_ILLEGAL_INSTRUCTION: + name = "illegal_instruction"; + break; + case SH4_EXCP_SLOT_ILLEGAL_INSTRUCTION: + name = "slot_illegal_instruction"; + break; + case SH4_EXCP_FPU_DISABLE: + name = "fpu_disable"; + break; + case SH4_EXCP_SLOT_FPU_DISABLE: + name = "slot_fpu"; + break; + case SH4_EXCP_DATA_WRITE: + name = "data_write"; + break; + case SH4_EXCP_DTLB_MISS_WRITE: + name = "dtlb_miss_write"; + break; + case SH4_EXCP_DTLB_VIOLATION_WRITE: + name = "dtlb_violation_write"; + break; + case SH4_EXCP_FPU: + name = "fpu_exception"; + break; + case SH4_EXCP_INITIAL_PAGE_WRITE: + name = "initial_page_write"; + break; + case SH4_EXCP_TRAPA: + name = "trapa"; + break; + default: + name = "???"; + break; + } + + return name; +} + #if defined(CONFIG_USER_ONLY) int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr) @@ -95,53 +147,8 @@ void superh_cpu_do_interrupt(CPUState *cs) } if (qemu_loglevel_mask(CPU_LOG_INT)) { - const char *expname; - switch (cs->exception_index) { - case SH4_EXCP_ADDR_ERROR: - expname = "addr_error"; - break; - case SH4_EXCP_TLB_MISS: - expname = "tlb_miss"; - break; - case SH4_EXCP_TLB_VIOLATION: - expname = "tlb_violation"; - break; - case SH4_EXCP_ILLEGAL_INSTRUCTION: - expname = "illegal_instruction"; - break; - case SH4_EXCP_SLOT_ILLEGAL_INSTRUCTION: - expname = "slot_illegal_instruction"; - break; - case SH4_EXCP_FPU_DISABLE: - expname = "fpu_disable"; - break; - case SH4_EXCP_SLOT_FPU_DISABLE: - expname = "slot_fpu"; - break; - case SH4_EXCP_DATA_WRITE: - expname = "data_write"; - break; - case SH4_EXCP_DTLB_MISS_WRITE: - expname = "dtlb_miss_write"; - break; - case SH4_EXCP_DTLB_VIOLATION_WRITE: - expname = "dtlb_violation_write"; - break; - case SH4_EXCP_FPU: - expname = "fpu_exception"; - break; - case SH4_EXCP_INITIAL_PAGE_WRITE: - expname = "initial_page_write"; - break; - case SH4_EXCP_TRAPA: - expname = "trapa"; - break; - default: - expname = do_irq ? "interrupt" : "???"; - break; - } - qemu_log("exception 0x%03x [%s] raised\n", - irq_vector, expname); + qemu_log("exception 0x%03x [%s] raised\n", irq_vector, + do_irq ? "interrupt" : sh4_exception_name(cs->exception_index)); log_cpu_state(cs, 0); } -- 2.55.0