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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e2583523asm2456199f8f.37.2026.10.20.20.18.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Oct 2026 20:18:22 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 32/33] target/tricore: Implement and register CPUClass::exception_name() Date: Wed, 21 Oct 2026 05:14:05 +0200 Message-ID: <20261021031407.24862-33-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com> References: <20261021031407.24862-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=aI5lOr9m c=1 sm=1 tr=0 ts=6ad82f01 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=M3mzNYHUzacmDIfs9B8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: FJ0cGm-bHy62PG-gr6ls-UcKWjtYEs5e X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX/r3nPZ5HdcE4 2uPKArfQ5gUftIbJekwpEDg9B/iVOtIYnKADMRBD5OPOk46d/3E/gK6d7yVe4SBJrzocG+2Z5Rr 6ou/fMxfTlzGkJ/94vADQJ12685u1aXfq/3v3erzmp9pHUOket55Lc+zruWfUSxdH1/vrjCUrzL tExvhhOZSB8NymqXKxlTxbDUKqIpVtZ89dx6e2qB/xuw6SxFSVYqrYf59GFOIwJIpopPn+mghQ8 MaL/EaVB21WAm+oKjOdEnJSiDb082Zam1zj/gLLdlnLcdfhCsy01VwO5SIQjKtjPxrxsFAKwLzs jT8gN6LqSiSnS1Ka7/qtbykLZjVmXhm8+0/nkhF8AKHqiAqI1/INiQJBntVRe90PZ56smKvOppu z4MlzhwjZZSzSgodzX75kbBg9Ty+DAMMBGRu/VIqnSkgGMT/DMogK/keXG0TDovL5s+lYiGIKCZ 2KNHtYILQHlYmDcat1w== X-Proofpoint-GUID: FJ0cGm-bHy62PG-gr6ls-UcKWjtYEs5e X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX/k0N6aq2rOEp I1Qm+3zkjk6yziinZC2jYy44tXWX5PbOTyyim9mVLnWbEhVKML6D7ZmHAcXLsFr746M4TzHI+to 17yjvAWLgWnmjThhYFueGhnjs7S35E8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210012 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Implement tricore_trap_name() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve TriCore trop numbers to names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/tricore/cpu.h | 2 ++ target/tricore/cpu.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 12e497d2a7a..fb8d2fd1011 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -178,6 +178,8 @@ enum { TRAPC_IRQ = 8 }; +const char *tricore_trap_name(int trap); + /* Class 0 TIN */ enum { TIN0_VAF = 0, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 84a05e3d363..632568a6544 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -36,6 +36,23 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs) return "tricore"; } +const char *tricore_trap_name(int trap) +{ + static const char * const trap_names[] = { + [TRAPC_MMU] = "mmu", + [TRAPC_PROT] = "prot", + [TRAPC_INSN_ERR] = "insn err", + [TRAPC_CTX_MNG] = "ctx mng", + [TRAPC_SYSBUS] = "sysbus", + [TRAPC_ASSERT] = "assert", + [TRAPC_SYSCALL] = "syscall", + [TRAPC_NMI] = "NMI", + [TRAPC_IRQ] = "IRQ", + }; + + return ARRAY_ELEM_OR_NULL(trap_names, trap) ?: "unknown"; +} + static void tricore_disas_set_info(const CPUState *cpu, disassemble_info *info) { CPUTriCoreState *env = cpu_env((CPUState *)cpu); @@ -240,6 +257,7 @@ static void tricore_cpu_class_init(ObjectClass *c, const void *data) resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL, &mcc->parent_phases); cc->class_by_name = tricore_cpu_class_by_name; + cc->exception_name = tricore_trap_name; cc->gdb_read_register = tricore_cpu_gdb_read_register; cc->gdb_write_register = tricore_cpu_gdb_write_register; -- 2.55.0