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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e258358c1sm2461142f8f.43.2026.10.20.20.15.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 20 Oct 2026 20:15:11 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Pierrick Bouvier Subject: [PATCH v2 08/33] target/hexagon: Register CPUClass::exception_name() handler Date: Wed, 21 Oct 2026 05:13:41 +0200 Message-ID: <20261021031407.24862-9-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com> References: <20261021031407.24862-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX7Zqv2NKw2Sy7 MM3xsdTRSaTPdFkTe/zRjzIkKlO6B5StrVAe9YrOjf1SJhADXrq76XFhSHYKntn6HVxskJkzx1W WrvLFsGxvQme3r1wqcJNUwSfZexQQEVVqWgice4zupjdFRanfcD/Ym2Wy3qJLS6ko3ersz8lXVA eB/7W8hhtSl4W4YYGoRaDeaKBITwnP6ijbzjFFnarFVZLGPRJOgj5u379BjkyikSCh1B/Iug2p4 6niMmx8OvwiDP/iGDU+jln09x4mHqqXreXAQuHiVMwIOiGHwtZZ+ifiirh3G/0Zph2BwvQTlvnZ zpAQ2Rf4oCWd1AbDtEYOYhK71DwI7yduSdQEUo7ejF8S2K1qXmChZa8FoMJqjvX9bsEWR1KWAuA yT87j4aWALNzHNETxiJ2b1QrIdILK3TahyvsBCBTVH3AqrwamWC7Q2wpA3T9ZYPqs1brrAAXsI2 KBZ9UwU/1pULUIa921Q== X-Proofpoint-ORIG-GUID: XtB2boJIPNIdMH1RDC3YTZroLgoBc-tE X-Proofpoint-GUID: XtB2boJIPNIdMH1RDC3YTZroLgoBc-tE X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAxMiBTYWx0ZWRfX8FkW8M1N3lJJ RRooi0k/9YtxMH8Gr9bQZ18W++Mme+MOSl+kcjn41DClIsE3ImS0zzzXpvfZHU8rgpVPwa/mrQg QuDhWrZAXpSgJmr2XO5cS0fkxrup6HM= X-Authority-Analysis: v=2.4 cv=NppE4MdJ c=1 sm=1 tr=0 ts=6ad82e44 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=L0AECS4D--PbZBcdiJkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210012 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Expose the hexagon event_name[] array via a hexagon_event_name() helper and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve Hexagon exception codes to names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Brian Cain --- target/hexagon/cpu_bits.h | 2 ++ target/hexagon/cpu.c | 34 ++++++++++++++++++++++++++++++++++ target/hexagon/hexswi.c | 30 +----------------------------- 3 files changed, 37 insertions(+), 29 deletions(-) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index a8fba4aa188..7d1bdfcbc71 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -61,6 +61,8 @@ enum hex_event { HEX_EVENT_INTF = 0x1f, }; +const char *hexagon_event_name(int event); + enum hex_cause { HEX_CAUSE_NONE = -1, HEX_CAUSE_RESET = 0x000, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index f20d6de6f63..962f00bc36c 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -318,6 +318,39 @@ void hexagon_debug(CPUHexagonState *env) hexagon_dump(env, stdout, CPU_DUMP_FPU); } +const char *hexagon_event_name(int event) +{ + static const char *event_name[] = { + [HEX_EVENT_RESET] = "HEX_EVENT_RESET", + [HEX_EVENT_IMPRECISE] = "HEX_EVENT_IMPRECISE", + [HEX_EVENT_PRECISE] = "HEX_EVENT_PRECISE", + [HEX_EVENT_TLB_MISS_X] = "HEX_EVENT_TLB_MISS_X", + [HEX_EVENT_TLB_MISS_RW] = "HEX_EVENT_TLB_MISS_RW", + [HEX_EVENT_TRAP0] = "HEX_EVENT_TRAP0", + [HEX_EVENT_TRAP1] = "HEX_EVENT_TRAP1", + [HEX_EVENT_FPTRAP] = "HEX_EVENT_FPTRAP", + [HEX_EVENT_DEBUG] = "HEX_EVENT_DEBUG", + [HEX_EVENT_INT0] = "HEX_EVENT_INT0", + [HEX_EVENT_INT1] = "HEX_EVENT_INT1", + [HEX_EVENT_INT2] = "HEX_EVENT_INT2", + [HEX_EVENT_INT3] = "HEX_EVENT_INT3", + [HEX_EVENT_INT4] = "HEX_EVENT_INT4", + [HEX_EVENT_INT5] = "HEX_EVENT_INT5", + [HEX_EVENT_INT6] = "HEX_EVENT_INT6", + [HEX_EVENT_INT7] = "HEX_EVENT_INT7", + [HEX_EVENT_INT8] = "HEX_EVENT_INT8", + [HEX_EVENT_INT9] = "HEX_EVENT_INT9", + [HEX_EVENT_INTA] = "HEX_EVENT_INTA", + [HEX_EVENT_INTB] = "HEX_EVENT_INTB", + [HEX_EVENT_INTC] = "HEX_EVENT_INTC", + [HEX_EVENT_INTD] = "HEX_EVENT_INTD", + [HEX_EVENT_INTE] = "HEX_EVENT_INTE", + [HEX_EVENT_INTF] = "HEX_EVENT_INTF", + }; + + return ARRAY_ELEM_OR_NULL(event_name, event) ?: "unknown"; +} + static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) { cpu_env(cs)->gpr[HEX_REG_PC] = value; @@ -841,6 +874,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data) &mcc->parent_phases); cc->class_by_name = hexagon_cpu_class_by_name; + cc->exception_name = hexagon_event_name; cc->dump_state = hexagon_dump_state; cc->set_pc = hexagon_cpu_set_pc; cc->get_pc = hexagon_cpu_get_pc; diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c index e7362b56650..19439658392 100644 --- a/target/hexagon/hexswi.c +++ b/target/hexagon/hexswi.c @@ -735,34 +735,6 @@ static void set_addresses(CPUHexagonState *env, uint32_t pc_offset, env->gpr[HEX_REG_PC] = evb | (exception_index << 2); } -static const char *event_name[] = { - [HEX_EVENT_RESET] = "HEX_EVENT_RESET", - [HEX_EVENT_IMPRECISE] = "HEX_EVENT_IMPRECISE", - [HEX_EVENT_PRECISE] = "HEX_EVENT_PRECISE", - [HEX_EVENT_TLB_MISS_X] = "HEX_EVENT_TLB_MISS_X", - [HEX_EVENT_TLB_MISS_RW] = "HEX_EVENT_TLB_MISS_RW", - [HEX_EVENT_TRAP0] = "HEX_EVENT_TRAP0", - [HEX_EVENT_TRAP1] = "HEX_EVENT_TRAP1", - [HEX_EVENT_FPTRAP] = "HEX_EVENT_FPTRAP", - [HEX_EVENT_DEBUG] = "HEX_EVENT_DEBUG", - [HEX_EVENT_INT0] = "HEX_EVENT_INT0", - [HEX_EVENT_INT1] = "HEX_EVENT_INT1", - [HEX_EVENT_INT2] = "HEX_EVENT_INT2", - [HEX_EVENT_INT3] = "HEX_EVENT_INT3", - [HEX_EVENT_INT4] = "HEX_EVENT_INT4", - [HEX_EVENT_INT5] = "HEX_EVENT_INT5", - [HEX_EVENT_INT6] = "HEX_EVENT_INT6", - [HEX_EVENT_INT7] = "HEX_EVENT_INT7", - [HEX_EVENT_INT8] = "HEX_EVENT_INT8", - [HEX_EVENT_INT9] = "HEX_EVENT_INT9", - [HEX_EVENT_INTA] = "HEX_EVENT_INTA", - [HEX_EVENT_INTB] = "HEX_EVENT_INTB", - [HEX_EVENT_INTC] = "HEX_EVENT_INTC", - [HEX_EVENT_INTD] = "HEX_EVENT_INTD", - [HEX_EVENT_INTE] = "HEX_EVENT_INTE", - [HEX_EVENT_INTF] = "HEX_EVENT_INTF" -}; - void hexagon_cpu_do_interrupt(CPUState *cs) { @@ -775,7 +747,7 @@ void hexagon_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "\t%s: event 0x%02x:%s, cause 0x%" PRIx32 "(%" PRIu32 ")\n", __func__, (unsigned)cs->exception_index, - event_name[cs->exception_index], env->cause_code, + hexagon_event_name(cs->exception_index), env->cause_code, env->cause_code); env->llsc_addr = ~0; -- 2.55.0