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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3674206d1f1sm9116156eec.28.2026.10.21.11.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 11:11:38 -0700 (PDT) Date: Wed, 21 Oct 2026 11:11:15 -0700 From: Jonathan Cameron To: Jason Gunthorpe Cc: Alexandre Ghiti , Albert Ou , Ard Biesheuvel , Arnd Bergmann , Catalin Marinas , Jonathan Corbet , David Sterba , Ilias Apalodimas , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-efi@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Randy Dunlap , Simon Glass , Shuah Khan , Nick Terrell , Will Deacon , Alexandre Ghiti , Conor Dooley , linux-integrity@vger.kernel.org, Palmer Dabbelt , patches@lists.linux.dev, Piotr =?ISO-8859-1?Q?Kr=F3l?= , Ross Philipson , Sami Tolvanen , Song Shuai Subject: Re: [PATCH v2 15/15] efi/arm64: Implement ARM64 DRTM in the stub Message-ID: <20261021111115.00004c5c@oss.qualcomm.com> In-Reply-To: <15-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> References: <0-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> <15-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ugMEB8RH-k1d_iuckQUJJ5vHuqYtsv-u X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA3MiBTYWx0ZWRfX9Gv4m+gh4AEl lI6dF3hB6OwtBem3LbhW+01AY0k+2OpEVKFlYjBin9vYXtrIA9bRP3xL4DBElNyFvqEA/L3b1e+ zp3wzrY++7c6aUcK6fFYRH+01FwEZNIe1lwteYx3UgtH9TQ7bnIQcbgyvl7onjC/wWWE0EW6nXr DbMxljqPrEhIIanowqFuu/bAU/mFNDMZFsxAu8gA+pB73Q8iaPipkqU92WOpuCbf0cQsQKCJ1GQ 4Eh8KpRXR4CPvC5rtzpZRFJMlxoqqM6wTSP9Rc/Gsr9L4bVNVrFEPZ2kmMs4uewGD3ounqG+307 z1vY5DN8PgDpDlnngb9YVZgPrdy2Sroapwu6FzweSVvG3FVLj4Ik+5XSmEQ4ryQEa9Kg5d+N2tb Txt56gllKZZwrIBk5SqKNZ9PQyR0pdKDZiOS44909tsqExQA3GtZUgSNc3rqQP3y2IA/I8HR/zc ZojmRs/5zv7bBCn9+JQ== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA3MiBTYWx0ZWRfXy/gNqbx34kPN QuiEZReRhXV4Y4/ZHoXfhvA/hEpBKQbj4tv7gh2/hZ5NtHQGAJeLm3uHd/CgWfCfmP7IBG1ZNNR KVb6iOZFw8/1LlwG8MnLViMXxFVwYcA= X-Proofpoint-ORIG-GUID: ugMEB8RH-k1d_iuckQUJJ5vHuqYtsv-u X-Authority-Analysis: v=2.4 cv=IPaXmQvG c=1 sm=1 tr=0 ts=6ad9005e cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=Ikd4Dj_1AAAA:8 a=Sk9Lk7371zlc0StAK_oA:9 a=CjuIK1q_8ugA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_05,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 spamscore=0 priorityscore=1501 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210072 On Fri, 2 Oct 2026 20:31:52 -0300 Jason Gunthorpe wrote: > Provide an implementation of the CONFIG_EFI_STUB_DRTM protocol for ARM64 > DEN0113 >= v1.1. > > First, it queries the FW for support and collects all the > information. This is needed to compute the extra_size, which comes > from FW reporting how much memory it needs during the launch for the > DLME Data and DCE-owned data. The generic stub ensures there is > trailing memory after Image for this. > > Then the DRTM_PARAMETERS launch structure is computed using the > offsets in the efi_info. > > Finally, the stub does ExitBootServices and calls the actual launch. > > The feature discovery process is deliberately fairly verbose to help > debug any FW weirdness in the field. Enable it with efi=debug > > It looks something like: > > EFI stub: DRTM: interface version 1.4 > EFI stub: DEBUG: DRTM: TPM algorithm 0xc, TPM hashing unavailable, PCR schemas 0x1 > EFI stub: DEBUG: DRTM: minimum DLME data 73728 bytes, Normal-world DCE 0 bytes > EFI stub: Decompressing Linux Kernel... > EFI stub: Generating empty DTB > EFI stub: Exiting boot services... > EFI stub: DEBUG: DRTM: will launch, selected launch features 0x0 > [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510] > > Eventually the launch'd kernel is going to require built in crypto > libraries that match what the FW is using so it can validate some of the > information left behind during early boot. Refuse to launch if these are > not built in and build in the most common ones from the ARM64_DRTM > kconfig. > > One nit, if the platform does not support SMC then using drtm=auto may > crash on the SMC op. As far as I can tell there is no way to discover SMC > support through EFI. Learning it from the ACPI FADT is doable and costs > about 250 lines of code. Ouch. Sounds like a must have if there is no easier way. > > Signed-off-by: Jason Gunthorpe One thing inline that confused me. Otherwise seems fine to me > diff --git a/drivers/firmware/efi/libstub/arm64-drtm.c b/drivers/firmware/efi/libstub/arm64-drtm.c > new file mode 100644 > index 00000000000000..2fc58babc3e7cb > --- /dev/null > +++ b/drivers/firmware/efi/libstub/arm64-drtm.c > @@ -0,0 +1,426 @@ > + > +/* True if SMCCC 1.0 or later is available. */ > +static bool efi_arm64_psci_smccc_compatible(void) > +{ > + struct arm_smccc_res res; > + s32 status; > + > + arm_smccc_1_1_smc(PSCI_0_2_FN_PSCI_VERSION, &res); A function that is meant to check for smccc 1.0 is using the smccc_1_1 namespaced calls? Maybe add a comment on why that is ok to do. Is anyone actually using SMCCC 1.0 on systems like this? I a bit surprised we don't have a common helper for this - I guess the version checks are often explicit in a particular driver being bound. > + if ((s32)res.a0 < 0) > + return false; > + > + if (PSCI_VERSION_MAJOR(res.a0) < 1) > + return false; > + > + arm_smccc_1_1_smc(PSCI_1_0_FN_PSCI_FEATURES, ARM_SMCCC_VERSION_FUNC_ID, > + &res); > + status = (s32)res.a0; > + if (status == PSCI_RET_NOT_SUPPORTED) { > + /* > + * SMCCC_VERSION was introduced by SMCCC 1.1, so firmware that > + * does not advertise that function through PSCI_FEATURES is > + * using the valid SMCCC 1.0 baseline. > + */ > + return true; > + } else if (status < 0) { > + return false; > + } else { > + u32 version; > + > + arm_smccc_1_1_smc(ARM_SMCCC_VERSION_FUNC_ID, &res); > + version = res.a0; > + if ((version >> 16) != 1 || version < ARM_SMCCC_VERSION_1_1) > + return false; > + } > + return true; > +} From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C52D5606A31A for ; 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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3674206d1f1sm9116156eec.28.2026.10.21.11.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 11:11:38 -0700 (PDT) Date: Wed, 21 Oct 2026 11:11:15 -0700 From: Jonathan Cameron To: Jason Gunthorpe Cc: Alexandre Ghiti , Albert Ou , Ard Biesheuvel , Arnd Bergmann , Catalin Marinas , Jonathan Corbet , David Sterba , Ilias Apalodimas , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-efi@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Randy Dunlap , Simon Glass , Shuah Khan , Nick Terrell , Will Deacon , Alexandre Ghiti , Conor Dooley , linux-integrity@vger.kernel.org, Palmer Dabbelt , patches@lists.linux.dev, Piotr =?ISO-8859-1?Q?Kr=F3l?= , Ross Philipson , Sami Tolvanen , Song Shuai Subject: Re: [PATCH v2 15/15] efi/arm64: Implement ARM64 DRTM in the stub Message-ID: <20261021111115.00004c5c@oss.qualcomm.com> In-Reply-To: <15-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> References: <0-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> <15-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) X-Archived-By: MIME-Version: 1.0 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA3MiBTYWx0ZWRfXy4H/oik8TBWc hTyVHUBDf+n856sqSSnSVWsSWJLd8/D1t+wFaCwb9a1c1Qxt9MJ5et3I0UA1qOnNljOiwn1f32t ZexCqPPsPtJIc2kJQDOS2IIoMsKZmwc= X-Authority-Analysis: v=2.4 cv=eJaGH3p1 c=1 sm=1 tr=0 ts=6ad9005c cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=Ikd4Dj_1AAAA:8 a=Sk9Lk7371zlc0StAK_oA:9 a=CjuIK1q_8ugA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-GUID: iEGOtqCaO1UnQq_rex79zDDUpjBXjc7C X-Proofpoint-ORIG-GUID: iEGOtqCaO1UnQq_rex79zDDUpjBXjc7C X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA3MiBTYWx0ZWRfX3IVmJXEHdgBq VendAFm1ijMtryLoIKZnlQlsvnk7x3jWCtjCIg91YBRjc6/C9X4h5GK/3ahym+kkfDa6UIM/OZl xKrONrzIZHSuKUuksq6Vvj4CXyXb5E2938IU3xPVsWwhQz2AH2ZgtQtN55exJdtBnN5+CZmJhcK apkGdarroonO6RFSSh7j3VVqKDJS57rh7kzjTv33P9MBGFemsgU8et/h8OHCNZNMXvOXaeu+sjn NUP5IXG4dNzO+pfsjOgD3xM8gCdpamE9GD/AwvbM4se3TBl59gExPZUa/TQKB4G72HJBUaSyl36 9DA89e9YpXrmQhTqDPGV3TXeMENdbCq4Lig8z1/h0CE+qf553deDnfwT3s3hpXD3SHAcHdWkAlp GGqn7NuOWLG73bctqzxm5QoEkTeVHwLm9JifT29IcmqCsxoq83Ig94+Rq3Lt606fN6XTLFLdGc1 NcsDZtlRmP4g5DEypkg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_05,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 adultscore=0 spamscore=0 clxscore=1015 bulkscore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210072 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261021_111142_344878_0B842379 X-CRM114-Status: GOOD ( 35.96 ) X-Spam-Score: -2.8 (--) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Fri, 2 Oct 2026 20:31:52 -0300 Jason Gunthorpe wrote: > Provide an implementation of the CONFIG_EFI_STUB_DRTM protocol for ARM64 > DEN0113 >= v1.1. > > First, it queries the FW for support and collects all the > information. This is needed to compute the extra_size, which comes > from FW reporting how much memory it needs during the launch for the > DLME Data and DCE-owned data. The generic stub ensures there is > trailing memory after Image for this. > > Then the DRTM_PARAMETERS launch structure is computed using the > offsets in the efi_info. > > Finally, the stub does ExitBootServices and calls the actual launch. > > The feature discovery process is deliberately fairly verbose to help > debug any FW weirdness in the field. Enable it with efi=debug > > It looks something like: > > EFI stub: DRTM: interface version 1.4 > EFI stub: DEBUG: DRTM: TPM algorithm 0xc, TPM hashing unavailable, PCR schemas 0x1 > EFI stub: DEBUG: DRTM: minimum DLME data 73728 bytes, Normal-world DCE 0 bytes > EFI stub: Decompressing Linux Kernel... > EFI stub: Generating empty DTB > EFI stub: Exiting boot services... > EFI stub: DEBUG: DRTM: will launch, selected launch features 0x0 > [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510] > > Eventually the launch'd kernel is going to require built in crypto > libraries that match what the FW is using so it can validate some of the > information left behind during early boot. Refuse to launch if these are > not built in and build in the most common ones from the ARM64_DRTM > kconfig. > > One nit, if the platform does not support SMC then using drtm=auto may > crash on the SMC op. As far as I can tell there is no way to discover SMC > support through EFI. Learning it from the ACPI FADT is doable and costs > about 250 lines of code. Ouch. Sounds like a must have if there is no easier way. > > Signed-off-by: Jason Gunthorpe One thing inline that confused me. Otherwise seems fine to me > diff --git a/drivers/firmware/efi/libstub/arm64-drtm.c b/drivers/firmware/efi/libstub/arm64-drtm.c > new file mode 100644 > index 00000000000000..2fc58babc3e7cb > --- /dev/null > +++ b/drivers/firmware/efi/libstub/arm64-drtm.c > @@ -0,0 +1,426 @@ > + > +/* True if SMCCC 1.0 or later is available. */ > +static bool efi_arm64_psci_smccc_compatible(void) > +{ > + struct arm_smccc_res res; > + s32 status; > + > + arm_smccc_1_1_smc(PSCI_0_2_FN_PSCI_VERSION, &res); A function that is meant to check for smccc 1.0 is using the smccc_1_1 namespaced calls? Maybe add a comment on why that is ok to do. Is anyone actually using SMCCC 1.0 on systems like this? I a bit surprised we don't have a common helper for this - I guess the version checks are often explicit in a particular driver being bound. > + if ((s32)res.a0 < 0) > + return false; > + > + if (PSCI_VERSION_MAJOR(res.a0) < 1) > + return false; > + > + arm_smccc_1_1_smc(PSCI_1_0_FN_PSCI_FEATURES, ARM_SMCCC_VERSION_FUNC_ID, > + &res); > + status = (s32)res.a0; > + if (status == PSCI_RET_NOT_SUPPORTED) { > + /* > + * SMCCC_VERSION was introduced by SMCCC 1.1, so firmware that > + * does not advertise that function through PSCI_FEATURES is > + * using the valid SMCCC 1.0 baseline. > + */ > + return true; > + } else if (status < 0) { > + return false; > + } else { > + u32 version; > + > + arm_smccc_1_1_smc(ARM_SMCCC_VERSION_FUNC_ID, &res); > + version = res.a0; > + if ((version >> 16) != 1 || version < ARM_SMCCC_VERSION_1_1) > + return false; > + } > + return true; > +} _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv