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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM3PEPF000265BF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9576 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Add xcp parameter to amdgpu_gfx_reset_mes_compute() so on an ASIC that supports compute partitioning, we can identify the partition's node ID and its master XCC. Pass this master XCC ID to MES when calling MES for suspend, detecting hung queues, and resume. Signed-off-by: Amber Lin --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 17 +++++++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- 6 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 0c1c8ae822d4..ef34f7b02d0e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2470,6 +2470,7 @@ static int amdgpu_gfx_reset_mes_kcq(struct amdgpu_device *adev, } int amdgpu_gfx_reset_mes_compute(struct amdgpu_device *adev, + struct amdgpu_xcp *xcp, struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence, struct amdgpu_usermode_queue *uq, @@ -2486,6 +2487,14 @@ int amdgpu_gfx_reset_mes_compute(struct amdgpu_device *adev, struct amdgpu_gfx_deferred_entry deferred_end[AMDGPU_MAX_COMPUTE_RINGS + 1]; int n_deferred = 0; int ring_err; + uint32_t xcc_mask, xcc_id = 0, xcp_id = 0; + + if (xcp) { + amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); + /* master xcc in the partition */ + xcc_id = ffs(xcc_mask) - 1; + xcp_id = xcp->id; + } guard(mutex)(&adev->gfx.mec.reset_mutex); /* stop the drm schedulers for all compute queues */ @@ -2493,7 +2502,7 @@ int amdgpu_gfx_reset_mes_compute(struct amdgpu_device *adev, /* suspend all will determine which queues are hung. * reset detect will return the array of bad queue doorbells */ - r = amdgpu_mes_suspend(adev, 0); + r = amdgpu_mes_suspend(adev, xcc_id); /* if suspend all success, it should no hang queue */ if (!r) { dev_dbg(adev->dev, "Suspend all succeeds. xcc_id %d\n", xcc_id); @@ -2503,7 +2512,7 @@ int amdgpu_gfx_reset_mes_compute(struct amdgpu_device *adev, goto fence_reset; } r = amdgpu_mes_detect_and_reset_hung_queues(adev, AMDGPU_RING_TYPE_COMPUTE, - true, &num_hung, adev->gfx.mec.mes_hung_db_array, 0); + true, &num_hung, adev->gfx.mec.mes_hung_db_array, xcc_id); if (r) { dev_dbg(adev->dev, "MES fails on detecting hung queues\n"); goto out; @@ -2551,7 +2560,7 @@ int amdgpu_gfx_reset_mes_compute(struct amdgpu_device *adev, n_deferred++; } /* reset any KFD queues */ - r = amdgpu_amdkfd_reset_mes_queue(adev, 0, queue_type, pipe, queue, + r = amdgpu_amdkfd_reset_mes_queue(adev, xcp_id, queue_type, pipe, queue, adev->gfx.mec.mes_hung_db_array[i]); if (r) goto out; @@ -2582,7 +2591,7 @@ int amdgpu_gfx_reset_mes_compute(struct amdgpu_device *adev, out: /* resume all will enable the non-hung queues */ - amdgpu_mes_resume(adev, 0); + amdgpu_mes_resume(adev, xcc_id); /* Now CP is running again — replay backed-up commands and ring * doorbells on each reset queue. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 5939e1fb3b24..26bbec8f92e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -664,6 +664,7 @@ bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev); void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev); int amdgpu_gfx_reset_mes_compute(struct amdgpu_device *adev, + struct amdgpu_xcp *xcp, struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence, struct amdgpu_usermode_queue *uq, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 1a2aa85c504e..7dfe6e83f8ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -153,7 +153,7 @@ static void amdgpu_userq_hang_detect_work(struct work_struct *work) int r; if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) - r = amdgpu_gfx_reset_mes_compute(adev, NULL, NULL, + r = amdgpu_gfx_reset_mes_compute(adev, NULL, NULL, NULL, queue, NULL, NULL); else r = userq_funcs->reset(queue); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 315dfd806d56..fdc0620ca67f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6932,7 +6932,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, { struct amdgpu_device *adev = ring->adev; - return amdgpu_gfx_reset_mes_compute(adev, ring, timedout_fence, NULL, NULL, NULL); + return amdgpu_gfx_reset_mes_compute(adev, NULL, ring, timedout_fence, NULL, NULL, NULL); } static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index d334fb805020..ec5ec1fd8b9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5254,7 +5254,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, { struct amdgpu_device *adev = ring->adev; - return amdgpu_gfx_reset_mes_compute(adev, ring, timedout_fence, NULL, NULL, NULL); + return amdgpu_gfx_reset_mes_compute(adev, NULL, ring, timedout_fence, NULL, NULL, NULL); } static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index ce67e56efa8c..0eb4081a5740 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -506,7 +506,7 @@ static int reset_queues_mes(struct device_queue_manager *dqm, struct queue *q) queue_input.remove_queue_after_reset = false; queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; /* pass the known bad queue info to the reset function */ - r = amdgpu_gfx_reset_mes_compute(adev, NULL, NULL, NULL, &num_hung, &queue_input); + r = amdgpu_gfx_reset_mes_compute(adev, dqm->dev->xcp, NULL, NULL, NULL, &num_hung, &queue_input); if (r) goto fail; pdd = kfd_get_process_device_data(q->device, q->process); -- 2.43.0