[PATCH 3/3] drm/amdgpu: Correct hung queue number for reset

[Amber Lin <amber.lin@amd.com>]

In an ASIC supporting multi-compute partition, the number of queues
varies with the compute partition mode. We need to adjust the hqd_info
offset to get the correct hung queues doorbell offset and hqd_info.

Signed-off-by: Amber Lin <amber.lin@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 54 +++++++++++++++++--------
 1 file changed, 37 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 58766b27e150..5bcab09b15c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -108,6 +108,24 @@ static inline u32 amdgpu_mes_get_hqd_mask(u32 num_pipe,
 
 static void amdgpu_mes_userq_notify_unmap_work_handler(struct work_struct *work);
 
+static int get_num_queues_per_xcp(struct amdgpu_device *adev, int num_xcps)
+{
+	int i, num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
+	u32 num_queues = 0;
+
+	for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
+		num_queues += hweight32(adev->mes.gfx_hqd_mask[i]);
+
+	for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++)
+		num_queues += hweight32(adev->mes.compute_hqd_mask[i]);
+
+	num_xcc /= num_xcps;
+	for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++)
+		num_queues += hweight32(adev->mes.sdma_hqd_mask[i]) * num_xcc;
+
+	return num_queues;
+}
+
 int amdgpu_mes_init(struct amdgpu_device *adev)
 {
 	int i, r, num_pipes, num_queues = 0;
@@ -222,21 +240,18 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 		goto error_doorbell;
 
 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {
-		/* When queue/pipe reset is done in MES instead of in the
-		 * driver, MES passes hung queues information to the driver in
-		 * hung_queue_hqd_info. Calculate required space to store this
-		 * information.
+		/* When queue/pipe reset is handled by MES instead of by the
+		 * driver, driver provides the buffer for MES to store the hung
+		 * queues information. Calculate required buffer size, which is
+		 * the number of maximum queues. This number varies with compute
+		 * partition mode. We allocate the biggest size, which is SPX,
+		 * num_xcps = 1.
 		 */
-		for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
-			num_queues += hweight32(adev->mes.gfx_hqd_mask[i]);
-
-		for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++)
-			num_queues += hweight32(adev->mes.compute_hqd_mask[i]);
-
-		for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++)
-			num_queues += hweight32(adev->mes.sdma_hqd_mask[i]) * num_xcc;
-
+		num_queues = get_num_queues_per_xcp(adev, 1);
 		adev->mes.hung_queue_hqd_info_offset = num_queues;
+		/* Double num_queues. The first half is to store doorbell offset
+		 * and the second half is to store hqd_info.
+		 */
 		adev->mes.hung_queue_db_array_size = num_queues * 2;
 	}
 
@@ -526,8 +541,9 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
 					    uint32_t xcc_id)
 {
 	struct mes_detect_and_reset_queue_input input;
-	u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[xcc_id];
-	int hqd_info_offset = adev->mes.hung_queue_hqd_info_offset, r, i;
+	u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[0];
+	int hqd_info_offset, r, i;
+	int num_xcps = 1;
 
 	if (!hung_db_num || !hung_db_array)
 		return -EINVAL;
@@ -537,8 +553,12 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
 	    (queue_type != AMDGPU_RING_TYPE_SDMA))
 		return -EINVAL;
 
+	if (adev->xcp_mgr)
+		num_xcps = adev->xcp_mgr->num_xcps;
+	hqd_info_offset = get_num_queues_per_xcp(adev, num_xcps);
+
 	/* Clear the doorbell array before detection */
-	memset(adev->mes.hung_queue_db_array_cpu_addr[xcc_id], AMDGPU_MES_INVALID_DB_OFFSET,
+	memset(adev->mes.hung_queue_db_array_cpu_addr[0], AMDGPU_MES_INVALID_DB_OFFSET,
 		adev->mes.hung_queue_db_array_size * sizeof(u32));
 	input.queue_type = queue_type;
 	input.detect_only = detect_only;
@@ -554,7 +574,7 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
 
 	*hung_db_num = 0;
 	/* MES passes hung queues' doorbell to driver */
-	for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) {
+	for (i = 0; i < hqd_info_offset; i++) {
 		/* Finding hung queues where db_array[i] is a valid doorbell */
 		if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) {
 			dev_dbg(adev->dev, "MES: hung queue doorbell 0x%x\n", db_array[i]);
-- 
2.43.0