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Thu, 22 Oct 2026 03:20:19 -0500 From: Jesse Zhang To: CC: , Christian Koenig , , , , , Jesse Zhang Subject: [PATCH v2 02/15] drm/amdgpu/gfx12: add a gfx engine reset Date: Thu, 22 Oct 2026 16:19:42 +0800 Message-ID: <20261022082011.331462-2-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20261022082011.331462-1-Jesse.Zhang@amd.com> References: <20261022082011.331462-1-Jesse.Zhang@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A805:EE_|DS5PPF78FC67EBA:EE_ X-MS-Office365-Filtering-Correlation-Id: d7808642-5438-4c40-7411-08df301554d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|1800799024|36860700016|23010399003|18002099003|10067099003|22082099003|261021121427099003|3023799007|261021123027099003|11063799006|261009223027099003|56012099006; X-Microsoft-Antispam-Message-Info: N1BNe/41VyFtQ4exUKoNZGPpLkNsnSdZOb0MAvMoHWHCfAt8bot/iD38uXkpdjp8NhJZHn0kiwYakEQ2vcO8+IzeiF4Lk4cxIn2ve7lwmRpk/9tsTUfjBcB3WTBebyjmDD0kmm0itQ/YeBGIc6xexZRxNj27m8RWWuT1FNZQrpNUbA6elBfjJv9CngZZYbg5CTAt6nee/zV1oM4VcjAMoQ1GSTf4h9eAQRYgNC4Iu/Akdm/ebN6iQ1SDOFZQqqtsgAMBye/9HQ9sSbQMWgWruWMkc+IlB6DaJcX6kciNHibFZxBJUn9SCVdERcMkT2kWn32wDuVoMu2fQ6DKzQ4c0pqpOAptFyX+LBn+yjH6gs2PlgqITrl6So/AWyloCZDKiJDjbS4jf/qaZFwxIybqX+wOOWMxuIhwaAIMEl8X5iUNqSzqGvOxBJ447yeZFQ8c/V7/vaT2tmTClzcXqb/+vYxXahUN4/946T2JZkq9wRatlwC75v5G9uapBzLgbdMZhBr5gs44CuxrJaTvQNc+NdeiMNXSrS+aNmoIbTQrr4pnUWWLN876Tn8OXYqu7uGUqp9ulYlvKK26prN1HI3Z3S32IeGl2Y8RVme2xtQpCTFz50J+rOE3P6gM94HcflQlcuLlMuQQV5m24vDYf3DL+5fWTivlW9apFcmVClLmoT1VyDTrqiG+bb0R1cFRmOOKoza/LCl8pZJM1r35sw4zPg== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A805.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF78FC67EBA X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Some hangs leave the gfx streaming engine of the CP front-end stuck, eg. waiting for packet data that never arrives. Neither a queue reset nor a pipe reset can stop it, so the recovery currently ends in a full GPU reset, and VRAM is lost. Implement the reset_engine callback for the graphics engine: - halt PFP/ME; - wait for the memory requests of the CP DMA to complete; - with CP_SOFT_RESET_CNTL.GFX_ONLY_SOFT_RESET and GFX_HQD_REG_RESET set, pulse GRBM_SOFT_RESET.SOFT_RESET_CPF/CPG. A CPF reset alone does not clear the stuck stream; - restart PFP/ME and restore CP_PFP_IB_CONTROL; - remap the kernel gfx queue through MES from its MQD backup. MEC and the compute part of CPF/CPG aren't reset, so the compute queues keep running. MES fetches its own queues through CPF, and a MES command in flight during the reset doesn't complete: hold the MES lock across the reset. A CP DMA request in flight during the reset leaves the ME busy after it, and MES then fails its next commands. Wait for those requests before the reset, and give up after the usual timeout: the DMA of a hung stream may never complete. Wait for them after the reset too, but not for the whole CP, as the halted PFP stays busy until it is restarted. If the CP doesn't go idle once PFP/ME run again, fail the reset so that a full reset follows. The reset also clears the HQDs of the gfx user queues, the caller has to handle them. The callback relies on the caller to only use it when the IP reports AMDGPU_RESET_TYPE_PER_ENGINE, which a later patch enables with MES and async gfx rings. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 129 +++++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index d334fb805020..dfc409e28914 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -274,6 +274,8 @@ static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); +static int gfx_v12_0_reset_engine(struct amdgpu_device *adev, + enum amdgpu_gfx_engine engine); static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance, int xcc_id); static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); @@ -959,6 +961,7 @@ static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, + .reset_engine = &gfx_v12_0_reset_engine, }; static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) @@ -3844,6 +3847,132 @@ static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } +/* The CP DMA and the interfaces its memory requests go through */ +#define GFX12_CP_STAT_MEM_BUSY (CP_STAT__DMA_BUSY_MASK | \ + CP_STAT__TCIU_BUSY_MASK | \ + CP_STAT__RCIU_BUSY_MASK | \ + CP_STAT__UTCL2IU_BUSY_MASK) + +/* + * Soft reset the gfx CP and restart PFP and ME. Returns 0, or -ETIMEDOUT if the + * CP doesn't go idle after PFP and ME are restarted. + */ +static int gfx_v12_0_soft_reset_gfx_cp(struct amdgpu_device *adev) +{ + u32 tmp, cntl, me_cntl, ib_control; + int i; + + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); + + /* MES fetches its queues through CPF: keep it out of the reset. */ + amdgpu_mes_lock(&adev->mes); + + me_cntl = RREG32_SOC15(GC, 0, regCP_ME_CNTL); + /* Cleared by the reset. */ + ib_control = RREG32_SOC15(GC, 0, regCP_PFP_IB_CONTROL); + + tmp = REG_SET_FIELD(me_cntl, CP_ME_CNTL, ME_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); + WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); + udelay(50); + + /* A CP DMA in flight during the reset leaves the ME busy after it. */ + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, regCP_STAT) & GFX12_CP_STAT_MEM_BUSY)) + break; + udelay(1); + } + + /* Without GFX_ONLY_SOFT_RESET, a CPF reset would also hit compute and MES. */ + cntl = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); + tmp = REG_SET_FIELD(cntl, CP_SOFT_RESET_CNTL, GFX_ONLY_SOFT_RESET, 1); + tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, GFX_HQD_REG_RESET, 1); + WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); + + /* A CPF reset alone leaves the streaming engine stuck. */ + tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); + tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_CPF, 1); + tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_CPG, 1); + WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); + udelay(50); + tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_CPF, 0); + tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_CPG, 0); + WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); + + WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, cntl); + + /* Not the whole CP: the halted PFP stays busy until restarted. */ + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, regCP_STAT) & GFX12_CP_STAT_MEM_BUSY)) + break; + udelay(1); + } + amdgpu_mes_unlock(&adev->mes); + + gfx_v12_0_set_pfp_ucode_start_addr(adev); + gfx_v12_0_set_me_ucode_start_addr(adev); + tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, + REG_GET_FIELD(me_cntl, CP_ME_CNTL, CE_HALT)); + WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); + WREG32_SOC15(GC, 0, regCP_PFP_IB_CONTROL, ib_control); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); + + tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); + WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); + for (i = 0; i < adev->usec_timeout; i++) { + if (!RREG32_SOC15(GC, 0, regCP_STAT)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +/* + * Reset the graphics engine: the CP front-end (CPF/CPG), PFP/ME and the gfx + * HQDs. MEC, MES and the compute queues keep running. + */ +static int gfx_v12_0_reset_engine(struct amdgpu_device *adev, + enum amdgpu_gfx_engine engine) +{ + int i, r; + + lockdep_assert_held(&adev->gfx.mec.reset_mutex); + + if (engine != AMDGPU_GFX_ENGINE_GFX) + return -EOPNOTSUPP; + + amdgpu_gfx_off_ctrl(adev, false); + + r = gfx_v12_0_soft_reset_gfx_cp(adev); + if (r) { + dev_err(adev->dev, "gfx CP still busy after reset, CP_STAT 0x%08x\n", + RREG32_SOC15(GC, 0, regCP_STAT)); + goto exit; + } + + /* Map the kernel gfx queue again: the reset cleared its HQD. */ + r = amdgpu_gfx_disable_kgq(adev, 0); + if (r) + goto exit; + + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + amdgpu_gfx_mqd_reset_restore(&adev->gfx.gfx_ring[i]); + r = amdgpu_gfx_enable_kgq(adev, 0); + if (r) + goto exit; + + r = gfx_v12_0_cp_gfx_start(adev); + +exit: + amdgpu_gfx_off_ctrl(adev, true); + return r; +} + static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) { uint64_t clock = 0; -- 2.50.1