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Thu, 22 Oct 2026 03:20:23 -0500 From: Jesse Zhang To: CC: , Christian Koenig , , , , , Jesse Zhang Subject: [PATCH v2 04/15] drm/amdgpu/gfx: add callbacks to read and restore the ring state of a gfx queue Date: Thu, 22 Oct 2026 16:19:44 +0800 Message-ID: <20261022082011.331462-4-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20261022082011.331462-1-Jesse.Zhang@amd.com> References: <20261022082011.331462-1-Jesse.Zhang@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A7FF:EE_|MW4PR12MB7482:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f832d11-16ea-4a5e-79be-08df3015552d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|23010399003|82310400026|376014|36860700016|1800799024|6133799003|22082099003|18002099003|10067099003|261021121427099003|261009223027099003|11063799006|56012099006; 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MES doesn't save them in the MQD either when the engine hangs. Add struct amdgpu_gfx_hqd_ptrs for that ring state, and gfx callbacks for the gfx IP, which knows its registers and the layout of its MQD: - read_gfx_hqd_ptrs() reads the ring state of the gfx HQD of a doorbell; - restore_gfx_mqd_ring() puts it in the MQD after the reset, for MES to map the queue again from it. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 8dc669e89db5..ba6dcea3f7db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -345,6 +345,17 @@ struct amdgpu_gfx_shadow_info { u32 eop_alignment; }; +/* Ring state of a gfx HQD that a gfx engine reset clears. */ +struct amdgpu_gfx_hqd_ptrs { + u32 doorbell_index; + u64 mqd_addr; /* the MQD loaded in the HQD */ + bool on_hqd; + u64 wptr; + u32 offset; + u32 csmd_rptr; + bool connected; /* the queue the pipe executes */ +}; + /* The engines of the GFX IP that can be reset on their own. */ enum amdgpu_gfx_engine { AMDGPU_GFX_ENGINE_GFX, @@ -386,6 +397,16 @@ struct amdgpu_gfx_funcs { /* reset one engine, leaving the other one running */ int (*reset_engine)(struct amdgpu_device *adev, enum amdgpu_gfx_engine engine); + /* read the ring state of the gfx HQD of a doorbell, if it has one */ + bool (*read_gfx_hqd_ptrs)(struct amdgpu_device *adev, u32 doorbell_index, + struct amdgpu_gfx_hqd_ptrs *ptrs); + /* + * write the ring state read by read_gfx_hqd_ptrs() into a gfx MQD; + * true if the work up to ptrs->wptr was dropped + */ + bool (*restore_gfx_mqd_ring)(struct amdgpu_device *adev, void *mqd, + u32 ring_size, + struct amdgpu_gfx_hqd_ptrs *ptrs); }; struct sq_work { -- 2.50.1