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Thu, 22 Oct 2026 03:20:30 -0500 From: Jesse Zhang To: CC: , Christian Koenig , , , , , Jesse Zhang Subject: [PATCH v2 07/15] drm/amdgpu/userq: add a helper to signal the fences of a queue up to a point Date: Thu, 22 Oct 2026 16:19:47 +0800 Message-ID: <20261022082011.331462-7-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20261022082011.331462-1-Jesse.Zhang@amd.com> References: <20261022082011.331462-1-Jesse.Zhang@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A803:EE_|LV3PR12MB9213:EE_ X-MS-Office365-Filtering-Correlation-Id: d91e75c0-96f1-4999-768f-08df30156367 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|23010399003|1800799024|36860700016|376014|82310400026|261021121427099003|56012099006|261009223027099003|11063799006|10067099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: Y4e0Xig+nd2oIA53ohrbB76pXICoYj6oxL5haxaeW7+JMs0rUIIjnvkCrzjZCsnlrQ81rSzyUDeTZM5/vtanyoszjawLXpZGOiSTZ9eTJ3AeJ3yN9MIz9LWuQRDTuYUPAme+m1yBqGUMH2f4VjkaSymjy3jzP8ionFcl+rvGPsyPzoBDnL0mLoBu+yh1PO8QApbgC2U2jfsEYdHR87X5JNyBpgjDvmjq6pQ/p9aWeExTRvtDeXnnBmD0+3sJ9G8J1yHHgLWFNm0TmxirBUiur+/PmyYgRMwvpy2fFOllPcEwMYY9pYKU4zHBJY0o+j0aog13Y8xZw9+gbMMWskNwrf5MwW0evWFMef4n6127sclRFf86mVvPBkZzPlL9nsm1W4BpmxmtiX9UyPjv9z8rAm19zNgBMteM7g+W7r2Y3TcddRmw9tN2PrDkWjVJ5E70tRqiV/0aRlDnlMvP1WQ9ZjaT+ndNv1bJ48JDJKR7bqQNJcqYOL+YwT5jhFLGKJhHjuFVkW/qidCIYu/qzDeEujcVi2cQlyR02BnQoV9pYXqQKQCAPKTFX2DqSVBAtQrfF+ek7nr9X4VX4PE59yGIOUKnoSipBZFTCNA4qzsy6sq3Bdxgc39EBDSBcW1tykIh5gpE9gdZ1ee0MSxhZ9tuVjDkfK+37T253K45ufI7107U/5lvEBKbrJ6ZHkneY6IZ6d/K77VM/bro1sBPTI9pYQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A803.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9213 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The fence value of a user queue is the write pointer of the queue when the work was submitted. amdgpu_userq_fence_driver_force_completion() signals all the fences of a queue, as after a reset that dropped all its work. Add amdgpu_userq_fence_driver_force_completion_with_seqno(), which only signals the fences of the work up to a write pointer, with an error, for a reset that drops only part of the work of a queue: the work submitted after that write pointer still runs. Signed-off-by: Jesse Zhang --- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 31 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 2 ++ 2 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index a2fa59a9609e..e76249c43b7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -459,6 +459,37 @@ amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq) } } +/* + * Signal the fences of @userq with a seqno up to @seqno with -ECANCELED, eg. + * when a reset dropped the work that would have signaled them. + */ +void +amdgpu_userq_fence_driver_force_completion_with_seqno(struct amdgpu_usermode_queue *userq, + u64 seqno) +{ + struct amdgpu_userq_fence_driver *fence_drv = userq->fence_drv; + struct amdgpu_userq_fence *fence; + unsigned long flags; + + if (!fence_drv) + return; + + spin_lock_irqsave(&fence_drv->fence_list_lock, flags); + list_for_each_entry(fence, &fence_drv->fences, link) { + if (fence->base.seqno > seqno) + break; + spin_lock(dma_fence_spinlock(&fence->base)); + if (!dma_fence_is_signaled_locked(&fence->base)) + dma_fence_set_error(&fence->base, -ECANCELED); + spin_unlock(dma_fence_spinlock(&fence->base)); + } + if (amdgpu_userq_fence_read(fence_drv) < seqno) + amdgpu_userq_fence_write(fence_drv, seqno); + spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); + + amdgpu_userq_fence_driver_process(fence_drv); +} + int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h index 0bd51616cef1..0407c8c2575f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h @@ -65,6 +65,8 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq); int amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv); void amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq); +void amdgpu_userq_fence_driver_force_completion_with_seqno(struct amdgpu_usermode_queue *userq, + u64 seqno); void amdgpu_userq_fence_driver_destroy(struct kref *ref); int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); -- 2.50.1