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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by LV8PEPF0000005D.mail.protection.outlook.com (10.167.245.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.15 via Frontend Transport; Thu, 22 Oct 2026 14:09:28 +0000 Received: from BLR-L1-SARUNKOD.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Thu, 22 Oct 2026 09:09:14 -0500 From: Sairaj Kodilkar To: "H. Peter Anvin" , "Joerg Roedel (AMD)" , "Mike Rapoport (Microsoft)" , Andrew Morton , Borislav Petkov , Dapeng Mi , Dave Hansen , Ethan Nelson-Moore , Ingo Molnar , Jakub Kicinski , Jeff Layton , "Jonathan Corbet" , Kiryl Shutsemau , Li RongQing , Marco Elver , Paolo Bonzini , Randy Dunlap , Rick Edgecombe , Robin Murphy , "Sairaj Kodilkar" , Sean Christopherson , "Shuah Khan" , Suravee Suthikulpanit , Thomas Gleixner , "Vasant Hegde" , Will Deacon , , , , , , Subject: [PATCH v6 6/7] KVM: SVM: Add support for AMD IOMMU Guest APIC Physical Processor Interrupt (GAPPI) Date: Thu, 22 Oct 2026 19:34:24 +0530 Message-ID: <20261022140425.27465-7-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261022140425.27465-1-sarunkod@amd.com> References: <20261022140425.27465-1-sarunkod@amd.com> X-Mailing-List: iommu@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PEPF0000005D:EE_|LY0PR12MB025421:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a181aaf-d50a-4679-89c2-08df304615f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|7416014|1800799024|376014|82310400026|261009223027099003|10067099003|56012099006|261021121427099003|18002099003|22082099003|261021123027099003|921020|11063799006; X-Microsoft-Antispam-Message-Info: 97hX7hva7lzqRzoikALyCcpAt8iwkJY96p1vK43u5FHaNbtp2M3l52E1PzuGciSkCF4pZNPqPEX/nVgxKY+dC8KN9qUldLE2bq8cKy/Ll8SNcitnG8ZjQkav4gIbxhpOju12llqWzuaDIQ1ASWCuBJlC3GaKdTX9Oa5f67yxl9T6wb/AGi6JP3j4y8AEpZdAvKzYfNDekoqgiKIJ/WqYY/2S5hKC6LrO0hzndTK4ETfrKWgoPzTURsJlOLn/jCK9CB/4E66Nriz6+u547z2EUXlDqhr/TWQByJtAEzEes0zav1qPn0A3wRVlc5r7OgiaUEetOMydQbDF83zt4SHdHfRC83AM2a9z59jWWkNzpxH3DCpcCBTINpJagg6pmn53/WAJfEH4Na1ylGzu5qoSABlk/b8O7BKSH3oxioNpgfxw3h/rcsKLxwXDVPDsAWZbXv/eZ5xZDhxsUst3DSdJfcq7bXlHx0tNJG9Ux3canDGjTgmGl3v0Nf2AI++xAOA/ftS8KMR9GZ/1QIZVEQS/ChQHJDHGnxLMDF4rom7Kodx+9mqQYW0wU5e2W27iYwYmi5LLzqq4vuXpcleyUmzQj1IEUkteb9WF1c2djfu5gde7r6DddII2vNB7Do15wGD5NykWyXYyANN73QvNyK/E+3aW27Vm354TA5d3+VF2EHE9iDG8TljryGqMZS4jk0VzMYM8gRyAL3R1Vs0b4gbkv59YBnuKUw9jVVShXNr1qFsAvTc6U70FsIsRGq5yoyNY X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(23010399003)(7416014)(1800799024)(376014)(82310400026)(261009223027099003)(10067099003)(56012099006)(261021121427099003)(18002099003)(22082099003)(261021123027099003)(921020)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Lv3Gw81nJBQS5kuVXZjoPN3r4KmNWqzBb8cvda3D4JkwnLmu6A6XZ0EJIY88MbAeJHf2XkKXRECQm7tSFY/1C0OEpEykPaisJKANi8pdB3aNheeD99Kiji0+X5y9Y4K42fX+9ylCaHSyvYUJKGYquCyMxZTY+MuTVaPfkCEsuvjS840hgrtULSCB5RCiRVPnGsHgkqYzmZG3xaL87NrMjz0yFbdfqNkpB4gfb5dxGEisLJpTygE+uro1hzKDhl0B8MwiVopS7ZeGotsPRytrDTzVGxqULQj6AV0T3YqB+1N+AYVhU7oPicm0sUNcJBjYMlAMuNvpCy2ar+fP03Ov4QC1GarcOF4Qc57T7if1ZDbGWDSRbPkeXpm8h9rWHvEGIsydTw0fvlR6WPLeVTCUUuw/De42migS63ADj9qd87TSQFSlXZ8DnM01AYsytxx6 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2026 14:09:28.3982 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a181aaf-d50a-4679-89c2-08df304615f9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: LV8PEPF0000005D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LY0PR12MB025421 With AVIC guest-mode interrupt remapping, device interrupts are posted into the guest vAPIC backing page by the IOMMU. When the vCPU is not running (IRTE[IsRun] = 0), KVM must still be notified to schedule it. The legacy path uses the GA log. GAPPI (Guest APIC Physical Processor Interrupt) is an alternative to the GA log mechanism provided by the AMD IOMMU. With GAPPI enabled, the IOMMU still updates the vAPIC backing page IRR, but the host wakeup notification is delivered as a physical APIC interrupt to IRTE[Destination], using IRTE[GATag][7:0] as the vector (POSTED_INTR_WAKEUP_VECTOR). SVM follows the Intel posted-interrupt wakeup model. Each pCPU maintains a list of blocked vCPUs that may be woken by a GAPPI delivery to that CPU. When a vCPU blocks while waiting for an interrupt, SVM enqueues it on the wakeup list of the pCPU on which it was previously running and passes that same pCPU's physical APIC ID to the IOMMU to program IRTE[Destination]. The rationale is that the vCPU is likely to run again on the same pCPU, which is common when vCPUs are pinned; targeting GAPPI notifications there reduces unnecessary VMEXITs from GAPPI deliveries on other CPUs. SVM registers the GAPPI handler via kvm_set_posted_intr_wakeup_handler(). On delivery, it walks the local vCPU list and wakes vCPUs with a pending IRR. All GAPPI logic is gated on amd_iommu_gappi. Without it, KVM and the IOMMU falls back to the legacy GA log mechanism for vCPU wakeup. Signed-off-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 64 +++++++++++++++++++++++++++++++++++------ arch/x86/kvm/svm/svm.c | 1 + arch/x86/kvm/svm/svm.h | 4 +++ 3 files changed, 61 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index b975f08825ce..baeca0ad8dfe 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -877,6 +877,8 @@ int avic_init_vcpu(struct vcpu_svm *svm) INIT_LIST_HEAD(&svm->ir_list); raw_spin_lock_init(&svm->ir_list_lock); + svm->gappi_cpu = 0; + if (!enable_apicv || !irqchip_in_kernel(vcpu->kvm)) return 0; @@ -895,6 +897,17 @@ void avic_vcpu_free(struct kvm_vcpu *vcpu) if (kvm_svm->avic_physical_id_table && avic_is_addressable_vcpu(vcpu)) WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], 0); + + if (amd_iommu_gappi) { + struct vcpu_svm *svm = to_svm(vcpu); + unsigned long flags; + + local_irq_save(flags); + + kvm_pi_disable_wakeup_handler(vcpu, svm->gappi_cpu); + + local_irq_restore(flags); + } } void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu) @@ -934,8 +947,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, * if AVIC is enabled/uninhibited in the future. */ struct amd_iommu_pi_data pi_data = { - .ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, - vcpu->vcpu_idx), .is_guest_mode = kvm_vcpu_apicv_active(vcpu), .vapic_addr = avic_get_backing_page_address(to_svm(vcpu)), .vector = vector, @@ -958,6 +969,12 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, * scheduled out, KVM will update the pCPU info when the vCPU * is awakened and/or scheduled in. See also avic_vcpu_load(). */ + if (amd_iommu_gappi) + pi_data.ga_tag = POSTED_INTR_WAKEUP_VECTOR; + else + pi_data.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, + vcpu->vcpu_idx); + entry = svm->avic_physical_id_entry; if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) { pi_data.apicid = entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; @@ -966,6 +983,9 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, pi_data.apicid = -1; pi_data.wakeup_intr = entry & AVIC_PHYSICAL_ID_ENTRY_WAKEUP_INTR; pi_data.is_running = false; + + if (amd_iommu_gappi) + pi_data.apicid = cpu_physical_id(svm->gappi_cpu); } ret = irq_set_vcpu_affinity(host_irq, &pi_data); @@ -1018,7 +1038,7 @@ enum avic_vcpu_action { }; static void avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int apicid, - enum avic_vcpu_action action) + int cpu, enum avic_vcpu_action action) { bool wakeup_intr = (action & AVIC_START_BLOCKING); bool is_running = apicid >= 0; @@ -1027,6 +1047,25 @@ static void avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int apicid, lockdep_assert_held(&svm->ir_list_lock); + if (action & AVIC_TOGGLE_ON_OFF) + /* + * When AVIC is disabled, IOMMU switches to legacy IRTE and + * does not genrate wakeup notification. Hence there is no + * need to add vCPU on wakeup list. This reduces the number of + * vCPUs on the list, effectively reducing interrupt handler + * time and avoiding spurious wakeup to the vCPU. + */ + goto skip_wakeup_handler; + + if (amd_iommu_gappi && is_running) { + kvm_pi_disable_wakeup_handler(vcpu, svm->gappi_cpu); + svm->gappi_cpu = cpu; /* Store cpu number as target for GAPPI */ + } else if (amd_iommu_gappi && wakeup_intr) { + apicid = cpu_physical_id(svm->gappi_cpu); + kvm_pi_enable_wakeup_handler(vcpu, svm->gappi_cpu); + } + +skip_wakeup_handler: /* * Here, we go through the per-vcpu ir_list to update all existing * interrupt remapping table entry targeting this vcpu. @@ -1093,7 +1132,7 @@ static void __avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu, WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); - avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, action); + avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, cpu, action); raw_spin_unlock_irqrestore(&svm->ir_list_lock, flags); } @@ -1135,7 +1174,7 @@ static void __avic_vcpu_put(struct kvm_vcpu *vcpu, enum avic_vcpu_action action) */ raw_spin_lock_irqsave(&svm->ir_list_lock, flags); - avic_update_iommu_vcpu_affinity(vcpu, -1, action); + avic_update_iommu_vcpu_affinity(vcpu, -1, -1, action); WARN_ON_ONCE(entry & AVIC_PHYSICAL_ID_ENTRY_WAKEUP_INTR); @@ -1183,7 +1222,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) /* * The vCPU was preempted while blocking, ensure its IRTEs are - * configured to generate GA Log Interrupts. + * configured to request host wakeup notification. */ if (!(WARN_ON_ONCE(!(entry & AVIC_PHYSICAL_ID_ENTRY_WAKEUP_INTR)))) return; @@ -1308,6 +1347,13 @@ static bool __init avic_want_avic_enabled(void) return true; } +bool avic_vcpu_irq_pending(struct kvm_vcpu *vcpu) +{ + struct vcpu_svm *svm = to_svm(vcpu); + + return kvm_lapic_find_highest_irr(&svm->vcpu) >= 0; +} + /* * Note: * - The module param avic enable both xAPIC and x2APIC mode. @@ -1351,6 +1397,8 @@ bool __init avic_hardware_setup(void) void avic_hardware_unsetup(void) { - if (avic) - amd_iommu_register_ga_log_notifier(NULL); + if (!avic) + return; + + amd_iommu_register_ga_log_notifier(NULL); } diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index c054803d4673..cd0d8e8c386e 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5352,6 +5352,7 @@ struct kvm_x86_ops svm_x86_ops __initdata = { .vcpu_put = svm_vcpu_put, .vcpu_blocking = avic_vcpu_blocking, .vcpu_unblocking = avic_vcpu_unblocking, + .vcpu_irq_pending = avic_vcpu_irq_pending, .update_exception_bitmap = svm_update_exception_bitmap, .get_feature_msr = svm_get_feature_msr, diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 29bde741874a..58d4e85e30fe 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -368,6 +368,9 @@ struct vcpu_svm { /* Guest GIF value, used when vGIF is not enabled */ bool guest_gif; + + /* GAPPI related fields */ + int gappi_cpu; }; struct svm_cpu_data { @@ -958,6 +961,7 @@ int avic_init_vcpu(struct vcpu_svm *svm); void avic_vcpu_free(struct kvm_vcpu *vcpu); void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); void avic_vcpu_put(struct kvm_vcpu *vcpu); +bool avic_vcpu_irq_pending(struct kvm_vcpu *vcpu); void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, -- 2.34.1