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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a210299910sm26512745e9.1.2026.10.22.14.53.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Oct 2026 14:53:16 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Edgar E. Iglesias" Subject: [PATCH v3 16/33] target/microblaze: Implement and register CPUClass::exception_name() Date: Thu, 22 Oct 2026 23:50:56 +0200 Message-ID: <20261022215115.19680-17-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261022215115.19680-1-philmd@oss.qualcomm.com> References: <20261022215115.19680-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: gZPo9cr6Xl36x91Js8hVLqrB6mz5GJLA X-Proofpoint-ORIG-GUID: gZPo9cr6Xl36x91Js8hVLqrB6mz5GJLA X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIyMDA4NyBTYWx0ZWRfX3W4VmOI2nXm+ HuVRy8JRCM27sUAwbVeLZz1wIrXeZmowm0FQQHMWldHq+CRTtHrKkT8viCjghBe5sV7mFNzEr9O WApUfmbx2FF2YclU69Qb723QYHlbiJY= X-Authority-Analysis: v=2.4 cv=G4OJgNk5 c=1 sm=1 tr=0 ts=6ada85ce cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=_ZqrUhsafL45AmjA-XwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIyMDA4NyBTYWx0ZWRfXwJ3G9joMwmr+ iAWt8DXd5iJlBA0LJZzILJfvt4Nu/EckMUQ7lxCI9IP7gWJNB6S+C8lcRSjdAdJk1JfmHpZShLZ EfymvxC2hcwEkQZ10bOFqGnfgyqylcOaBSE2oTiMtcWvEOZY7VLHWxlM5syTbduTPQVgBvc5D3m q5eK46MTAr7YhUStgd3TA3hyrDYYcTaaIluGJbjrM132PCKAUP0+7fHK09ndzbLmOuuVg/IXeXu MPfi5IxUSjofsV0unrnaGhRSp5aYR0PMOBnbjdpsLsWpVaJm3+dAeNIkTfiNrqucpOaY2192xkY eb6zHn8+xamRJVU1Q5nw8ubS5wfjDqQ6Nyx9FIqWAHCGv0QOo1m44Fl/FHfnDZr57WW01Ixanzo iHItD1KuxeJphVZ+Q9g325WuWjhGCrpzdpwzsGjbYDKeT7N/iuOQgc6z9lpOta0sQC2MeEbqaof WTGlyzvokvuQvF6JxOw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-22_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610220087 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Implement microblaze_exception_name() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve MicroBlaze exception codes to names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/microblaze/cpu.h | 2 ++ target/microblaze/cpu.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b9602f72b94..fc2783693e3 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -36,6 +36,8 @@ typedef struct CPUArchState CPUMBState; #define EXCP_HW_BREAK 4 #define EXCP_HW_EXCP 5 +const char *microblaze_exception_name(int excp); + /* MicroBlaze-specific interrupt pending bits. */ #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 389a5124b12..a3d92a35d33 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -23,6 +23,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/cutils.h" #include "qapi/error.h" #include "cpu.h" #include "qemu/module.h" @@ -79,6 +80,19 @@ static const struct { /* If no specific version gets selected, default to the following. */ #define DEFAULT_CPU_VERSION "10.0" +const char *microblaze_exception_name(int excp) +{ + static const char * const excp_names[] = { + [EXCP_MMU] = "mmu", + [EXCP_IRQ] = "irq", + [EXCP_SYSCALL] = "syscall", + [EXCP_HW_BREAK] = "hw break", + [EXCP_HW_EXCP] = "hw excp", + }; + + return STR_ARRAY_ELEM_OR_NULL(excp_names, excp) ?: "unknown"; +} + static void mb_cpu_set_pc(CPUState *cs, vaddr value) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); @@ -469,6 +483,7 @@ static void mb_cpu_class_init(ObjectClass *oc, const void *data) &mcc->parent_phases); cc->class_by_name = mb_cpu_class_by_name; + cc->exception_name = microblaze_exception_name; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; cc->get_pc = mb_cpu_get_pc; -- 2.55.0