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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a211bda21dsm12016075e9.11.2026.10.22.14.54.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Oct 2026 14:54:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org Subject: [PATCH v3 23/33] target/riscv: Register CPUClass::exception_name() handler Date: Thu, 22 Oct 2026 23:51:03 +0200 Message-ID: <20261022215115.19680-24-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261022215115.19680-1-philmd@oss.qualcomm.com> References: <20261022215115.19680-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=V7LoQuni c=1 sm=1 tr=0 ts=6ada8601 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=y9j7XMdMAJhvWi9Kj2cA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIyMDA4NyBTYWx0ZWRfX4tfUKtMXIHZW nQPTYHn2SBJs9w21duMfzWHIzLNrDEMnAGC5wYXTfXG6Sf0525gfo5i5zjM4UMxMNY+vMHMT2zM B5Ctn5shVh+dleXELk3DJzv2Zg55KE0= X-Proofpoint-GUID: na4PQxhm8OkSMSv0DEB4QyNEIya-dikA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIyMDA4NyBTYWx0ZWRfX1rpDUgXOF027 sw07QnIvq39vLmK07788XouN4atkQGsKjBM8COETXdssmXEFfvq1oP59q+Iv0nzTHQ3IFaaFdpJ obDDkkuVimR1y9BXSCYohPgXEqmcvt5eQH7StTCOpVtVdJAUV87NJDHsf2oFIqYZxWvaaCk2gBD eblyGw10OOWbX29bXg0zXjrbM6geUnbSLI7diqTEDO4m/3wdMG0rUQCu86acCswAPJXeMZ6mhcS t78mnhlLcglnSYPNJSYUxdL4cz0B3r8zU/PSTMR3lQjgbWGlBb8UZO4jTfG0cTf1UeeEVWPB5fu +O2NCNUTvLYftX9qzvGDDIToxgwXLtcfgmc3/51nXmUI7NZUYEGRtCyEwsDzdJHia4a8M1DPvhk SrfocH1vUFgU6DdhxY4V1IpLHMLl32ND0gUNP1TwScE2pGCoDwG3uAnWJ3yKbENNSNHOeLRLWx5 bKPs1Eo96irTjwc9vYg== X-Proofpoint-ORIG-GUID: na4PQxhm8OkSMSv0DEB4QyNEIya-dikA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-22_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610220087 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Factor riscv_excp_name() and riscv_intr_name() out of riscv_cpu_get_trap_name(). Register riscv_excp_name() as the CPUClass::exception_name() handler, so the common exception logging can resolve RISCV exception codes to names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 20 ++++++++++---------- target/riscv/tcg/op_helper.c | 2 +- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b65d6319940..49a1186bdbb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -672,6 +672,7 @@ G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +const char *riscv_excp_name(int excp); char *riscv_isa_string(RISCVCPU *cpu); int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 08a4d14ea1f..e1652bd2a40 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qemu/qemu-print.h" #include "qemu/ctype.h" #include "qemu/log.h" @@ -398,6 +399,11 @@ static const char * const riscv_excp_names[] = { [RISCV_EXCP_SEMIHOST] = "semihost", }; +const char *riscv_excp_name(int excp) +{ + return STR_ARRAY_ELEM_OR_NULL(riscv_excp_names, excp) ?: "unknown"; +} + static const char * const riscv_intr_names[] = { [IRQ_U_SOFT] = "u_software", [IRQ_S_SOFT] = "s_software", @@ -417,17 +423,10 @@ static const char * const riscv_intr_names[] = { const char *riscv_cpu_get_trap_name(uint64_t cause, bool async) { - if (async) { - if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) { - return riscv_intr_names[cause]; - } - } else { - if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) { - return riscv_excp_names[cause]; - } - } + const char *name = async ? STR_ARRAY_ELEM_OR_NULL(riscv_intr_names, cause) + : STR_ARRAY_ELEM_OR_NULL(riscv_excp_names, cause); - return "(unknown)"; + return name ?: "unknown"; } void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) @@ -3128,6 +3127,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data) &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name; + cc->exception_name = riscv_excp_name; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->get_pc = riscv_cpu_get_pc; diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index b8b3e43ccd5..f85f5cd83c9 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -41,7 +41,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, CPUState *cs = env_cpu(env); trace_riscv_exception(exception, - riscv_cpu_get_trap_name(exception, false), + riscv_excp_name(exception), env->pc); cs->exception_index = exception; -- 2.55.0