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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a2123613easm4750465e9.5.2026.10.22.14.52.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Oct 2026 14:52:08 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , qemu-arm@nongnu.org Subject: [PATCH v3 07/33] target/arm: Register CPUClass::exception_name() handler Date: Thu, 22 Oct 2026 23:50:47 +0200 Message-ID: <20261022215115.19680-8-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261022215115.19680-1-philmd@oss.qualcomm.com> References: <20261022215115.19680-1-philmd@oss.qualcomm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=V7LoQuni c=1 sm=1 tr=0 ts=6ada858b cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=QvePOBYGvqDf6_zMoJUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIyMDA4NyBTYWx0ZWRfXzThjY2EU7cg1 yYmzNVsjKvHIB3SJQd7Mzfl9UjnxClyzAsE4FqRRrnDH4qG78Rq1R2QcRxyITzeyVBE6L2A+/r4 GdgrOpbnZxQbAjnVf85igTsD48IMqiI= X-Proofpoint-GUID: oT409UhblVDGXOCuV5JZuoIgSMbnJThu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIyMDA4NyBTYWx0ZWRfX2q++VN4A+wS+ OplT1tuPeRTqQYPDhYWEqrBaZawaF+D+ep+6aHHc13mYX2WyjA0RsK0qx2jrL34u6bKSVYl0c5w Y+SD0TSTzdVuU40V5j6vUaU7aOOf3A0wTOqwZDY8VwZs9L8co/pTaNofOV0AOfrPO/tDwbDY71P wsHFdji6VbDK24ZYq0ECgwjxs9uIyLrAw1Z6zaCqt9mjlLDvSmMe1hIhSkDys/oaEjuM3mU3I4+ GBQivV7IwsqjweT3vCgKveu7mpO3KPntjYbasw697lCenm2APBtQAwA+kY0yXrZK4MbXr9lAZLa XYydRFM/M7SrMZqCFELZDriTxwTJslVg+SddoRtn3+FmLs9a5mkMFUZ09jMT8hL5PfMWFc78HVL hU+zKG9NboS6H09uPQfTx9J3lDmPNQXSLyoY75Hjeh3kCodQNyfONjgLi+Cxd5j+GMubQtt4PHc 9LTV8BOw1dBS11eOAlg== X-Proofpoint-ORIG-GUID: oT409UhblVDGXOCuV5JZuoIgSMbnJThu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-22_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610220087 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Factor arm_exception_name() out of arm_log_exception() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve ARM exception codes to names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/arm/cpu.h | 4 ++- target/arm/cpu.c | 1 + target/arm/helper.c | 77 ++++++++++++++++++++++----------------------- 3 files changed, 42 insertions(+), 40 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a0355ba9e1a..add993ef101 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -65,7 +65,9 @@ #define EXCP_VINMI 27 #define EXCP_VFNMI 28 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */ -/* NB: add new EXCP_ defines to the array in arm_log_exception() too */ +/* NB: add new EXCP_ defines to the array in arm_exception_name() too */ + +const char *arm_exception_name(int excp); #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 81ec1ce21c6..8efbf673a92 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2647,6 +2647,7 @@ static void arm_cpu_class_init(ObjectClass *oc, const void *data) &acc->parent_phases); cc->class_by_name = arm_cpu_class_by_name; + cc->exception_name = arm_exception_name; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; cc->get_pc = arm_cpu_get_pc; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7ac21108d1c..b540705e638 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/cutils.h" #include "trace.h" #include "cpu.h" #include "internals.h" @@ -8841,46 +8842,8 @@ void arm_log_exception(CPUState *cs) int idx = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { - const char *exc = NULL; - static const char * const excnames[] = { - [EXCP_UDEF] = "Undefined Instruction", - [EXCP_SWI] = "SVC", - [EXCP_PREFETCH_ABORT] = "Prefetch Abort", - [EXCP_DATA_ABORT] = "Data Abort", - [EXCP_IRQ] = "IRQ", - [EXCP_FIQ] = "FIQ", - [EXCP_BKPT] = "Breakpoint", - [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", - [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", - [EXCP_HVC] = "Hypervisor Call", - [EXCP_HYP_TRAP] = "Hypervisor Trap", - [EXCP_SMC] = "Secure Monitor Call", - [EXCP_VIRQ] = "Virtual IRQ", - [EXCP_VFIQ] = "Virtual FIQ", - [EXCP_SEMIHOST] = "Semihosting call", - [EXCP_NOCP] = "v7M NOCP UsageFault", - [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", - [EXCP_STKOF] = "v8M STKOF UsageFault", - [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", - [EXCP_LSERR] = "v8M LSERR UsageFault", - [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", - [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", - [EXCP_VSERR] = "Virtual SERR", - [EXCP_GPC] = "Granule Protection Check", - [EXCP_NMI] = "NMI", - [EXCP_VINMI] = "Virtual IRQ NMI", - [EXCP_VFNMI] = "Virtual FIQ NMI", - [EXCP_MON_TRAP] = "Monitor Trap", - }; - - if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { - exc = excnames[idx]; - } - if (!exc) { - exc = "unknown"; - } qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", - idx, exc, cs->cpu_index); + idx, arm_exception_name(idx), cs->cpu_index); } } @@ -9967,6 +9930,42 @@ void arm_cpu_do_interrupt(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ +const char *arm_exception_name(int excp) +{ + static const char * const excnames[] = { + [EXCP_UDEF] = "Undefined Instruction", + [EXCP_SWI] = "SVC", + [EXCP_PREFETCH_ABORT] = "Prefetch Abort", + [EXCP_DATA_ABORT] = "Data Abort", + [EXCP_IRQ] = "IRQ", + [EXCP_FIQ] = "FIQ", + [EXCP_BKPT] = "Breakpoint", + [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", + [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", + [EXCP_HVC] = "Hypervisor Call", + [EXCP_HYP_TRAP] = "Hypervisor Trap", + [EXCP_SMC] = "Secure Monitor Call", + [EXCP_VIRQ] = "Virtual IRQ", + [EXCP_VFIQ] = "Virtual FIQ", + [EXCP_SEMIHOST] = "Semihosting call", + [EXCP_NOCP] = "v7M NOCP UsageFault", + [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", + [EXCP_STKOF] = "v8M STKOF UsageFault", + [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", + [EXCP_LSERR] = "v8M LSERR UsageFault", + [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", + [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", + [EXCP_VSERR] = "Virtual SERR", + [EXCP_GPC] = "Granule Protection Check", + [EXCP_NMI] = "NMI", + [EXCP_VINMI] = "Virtual IRQ NMI", + [EXCP_VFNMI] = "Virtual FIQ NMI", + [EXCP_MON_TRAP] = "Monitor Trap", + }; + + return STR_ARRAY_ELEM_OR_NULL(excnames, excp) ?: "unknown"; +} + uint64_t arm_sctlr(CPUARMState *env, int el) { /* Only EL0 needs to be adjusted for EL1&0 or EL2&0 or EL3&0 */ -- 2.55.0