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Sat, 24 Oct 2026 21:03:42 -0700 (PDT) Received: from at-Standard-PC-Q35-ICH9-2009 ([106.221.76.40]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-198a32ff780sm11635283c88.22.2026.10.24.21.03.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 21:03:41 -0700 (PDT) From: Atharva Tiwari To: Cc: Andre Eikmeyer , Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H. Peter Anvin" , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Kenneth Feng , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Atharva Tiwari , linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), platform-driver-x86@vger.kernel.org (open list:X86 PLATFORM DRIVERS) Subject: [PATCH 10/13] drm/amdgpu: Catch register access while GMUX keeps the GPU off Date: Sat, 24 Oct 2026 23:59:46 -0400 Message-ID: <20261025040046.1602-11-atharvatiwarilinuxdev@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261025040046.1602-1-atharvatiwarilinuxdev@gmail.com> References: <20261025040046.1602-1-atharvatiwarilinuxdev@gmail.com> X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Andre Eikmeyer As mentioned previous any access to the GPU when the GMUX has shut off the rails results in a CPU CATTER, skip and report any register access after the GPU was runtime suspended for GMUX power-off. Signed-off-by: Andre Eikmeyer --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 ++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 24 +++++++++++++++++++ 4 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 6fd607587..ac8dfc3ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -881,6 +881,8 @@ struct amdgpu_device { /* enable runtime pm on the device */ bool in_runpm; bool has_pr3; + /* GMUX has cut power, any register access would hang the PEG link */ + bool gmux_off; bool ucode_sysfs_en; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c1f196242..8185934b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -946,6 +946,11 @@ bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) if (adev->no_hw_access) return true; + if (unlikely(READ_ONCE(adev->gmux_off))) { + WARN_RATELIMIT(1, "%s: register access while powered off by GMUX\n", + dev_name(adev->dev)); + return true; + } #ifdef CONFIG_LOCKDEP /* * This is a bit complicated to understand, so worth a comment. What we assert diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 5ad7b6dd8..135798c76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2932,6 +2932,9 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev) amdgpu_device_baco_enter(adev); } + if (adev->pm.rpm_mode == AMDGPU_RUNPM_GMUX) + WRITE_ONCE(adev->gmux_off, true); + dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); return 0; @@ -2960,6 +2963,8 @@ static int amdgpu_pmops_runtime_resume(struct device *dev) if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) return -EINVAL; + WRITE_ONCE(adev->gmux_off, false); + /* Avoids registers access if device is physically gone */ if (!pci_device_is_present(adev->pdev)) adev->no_hw_access = true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 7468855c1..bb5dbeb7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -594,6 +594,9 @@ u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr) void __iomem *pcie_data_offset; u32 r; + if (amdgpu_device_skip_hw_access(adev)) + return 0; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); @@ -677,6 +680,12 @@ u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr) void __iomem *pcie_data_offset; u64 r; + if (amdgpu_device_skip_hw_access(adev)) + return 0; + + if (amdgpu_device_skip_hw_access(adev)) + return 0; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); @@ -706,6 +715,9 @@ u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr) void __iomem *pcie_data_offset; u64 r; + if (amdgpu_device_skip_hw_access(adev)) + return 0; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) @@ -762,6 +774,9 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, void __iomem *pcie_index_offset; void __iomem *pcie_data_offset; + if (amdgpu_device_skip_hw_access(adev)) + return; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); @@ -784,6 +799,9 @@ void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, void __iomem *pcie_index_hi_offset; void __iomem *pcie_data_offset; + if (amdgpu_device_skip_hw_access(adev)) + return; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) @@ -832,6 +850,9 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, void __iomem *pcie_index_offset; void __iomem *pcie_data_offset; + if (amdgpu_device_skip_hw_access(adev)) + return; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); @@ -861,6 +882,9 @@ void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, void __iomem *pcie_index_hi_offset; void __iomem *pcie_data_offset; + if (amdgpu_device_skip_hw_access(adev)) + return; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) -- 2.55.0